Read/Write BRAM in HLS
This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…
AXI4 Memory Mapped I/O in HLS
This blog briefly explains the AXI4 Memory Mapped I/O protocol. The memory-mapped system is a common technique to access I/O…
One-Shot in HLS
A one-shot is a logic circuit with two states, of which only one is stable. This post explains how to…
Logic Circuit Design with Xilinx Vitis-HLS
High-Level Synthesis increases the logic design abstraction level from RTL to the C-like high-level description. This higher abstraction level helps…
Reducing II in HLS: Conditional Registers vs Conditional Variables
Reducing pipelined loops’ initiation-interval is the main goal of optimising an algorithm in HLS. Using conditional registers inside a pipelined-loop…
SCII Design Approach in HLS
SCII design approach is introduced in the “High-Level Synthesis for FPGA” course for the first time. “High-Level Synthesis for FPGA…
Stepper Motor Controller in High-Level Synthesis
The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA. To achieve…
Reducing II in HLS: Loop Interchange
Abstract: This blog shows how the loop interchange optimisation technique in HLS can improve the design performance. If you would…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation
Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster.
A four-digit up/down counter on BASYS-3 FPGA Board Using Vitis-2020.1
The goal of this design is very similar to that of this post. Here, we are going to have a…