Read/Write BRAM in HLS
This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…
This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…
This blog briefly explains the AXI4 Memory Mapped I/O protocol. The memory-mapped system is a common technique to access I/O…
A one-shot is a logic circuit with two states, of which only one is stable. This post explains how to…
High-Level Synthesis increases the logic design abstraction level from RTL to the C-like high-level description. This higher abstraction level helps…
Reducing pipelined loops’ initiation-interval is the main goal of optimising an algorithm in HLS. Using conditional registers inside a pipelined-loop…
SCII design approach is introduced in the “High-Level Synthesis for FPGA” course for the first time. “High-Level Synthesis for FPGA…
The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA. To achieve…
Abstract: This blog shows how the loop interchange optimisation technique in HLS can improve the design performance. If you would…
Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster.
The goal of this design is very similar to that of this post. Here, we are going to have a…