Reducing II in HLS: Loop Interchange
Abstract: This blog shows how the loop interchange optimisation technique in HLS can improve the design performance. If you would…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation
Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster.
A four-digit up/down counter on BASYS-3 FPGA Board Using Vitis-2020.1
The goal of this design is very similar to that of this post. Here, we are going to have a…
Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model
In this model, an application code is divided into two parts: host code and kernels. Kernels are the tasks that…