Abstract: This blog shows how the loop interchange optimisation technique in HLS can improve the design performance. If you would like to learn how to …
Reducing II in HLS: Loop Interchange
November 2020
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation
In the previous blog, I explained how to implement the image thresholding example in Vitis for ZynqMPSOC. Here, I am going to optimise the kernel …
A four-digit up/down counter on BASYS-3 FPGA Board Using Vitis-2020.1
The goal of this design is very similar to that of this post. Here, we are going to have a 4-digit BCD counter. The following …
Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model
The Xilinx Vitis toolset uses the OpenCL programming model to support heterogeneous computing.In this model, an application code is divided into two parts: host code …