Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL

Support Vector Machine on Zynq (Zybo-Z7-20)

August 23, 2021 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, OpenCL

Vitis 2021.1 Embedded Platform for Zybo-Z7-20

August 15, 2021 — 0 Comments

Embedded System, Hardware Design, High-Level Synthesis, OpenCL

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2

August 14, 2021 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, High-Level Synthesis, OpenCL

How to create Zybo-Z7-20 Vitis Hardware Accelerator Platform

August 13, 2021 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL

Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation

November 13, 2020 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL

Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model

November 4, 2020 — 0 Comments

Embedded System, Hardware Design, High-Level Synthesis, OpenCL

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1

October 6, 2020 — 1 Comment

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL, Software

Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Ports

December 2, 2019 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL

Fundamentals of High-Level Synthesis – Part 4: Dependency, Concurrency and parallelism

November 18, 2019 — 0 Comments

Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL, Software

Fundamentals of High-Level Synthesis Part 3: From Concurrency to Parallelism (Map Pattern)

November 10, 2019 — 1 Comment