Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation
Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster.
Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model
In this model, an application code is divided into two parts: host code and kernels. Kernels are the tasks that…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Creating the Ulra96v2 platform in the Xilinx Vitis 2020.1 has…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Ports
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course In this blog, I am going to explain…
Fundamentals of High-Level Synthesis – Part 4: Dependency, Concurrency and parallelism
In the last two blogs, I explicitly talked about concurrency and parallelism. I also explained the dependency. However, the dependency…
Fundamentals of High-Level Synthesis Part 3: From Concurrency to Parallelism (Map Pattern)
In the previous blog, I explained the difference between concurrency and parallelism concepts in high-level synthesis. Whereas concurrency is a concept…
Embedded Hardware Accelerator with Xilinx Vitis: Part 1: Concept of Platform
FPGA-based accelerator design flow is at the stage that software engineers can benefit from without an in-depth knowledge of hardware…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1 Creating…
How to Install pocl on Jetson TX1
Installation: Download and install llvm+clang from http://releases.llvm.org/6.0.0/clang+llvm-6.0.0-aarch64-linux-gnu.tar.xz Download and install hwloc v1.0 or newer from https://www.open-mpi.org/software/hwloc/v1.0/ Download and install ocl-icd from…
Synthesis Tools
Goal General view of synthesis tools Credit This work has been done under the ENPOWER project (funded by EPSRC) at University…