DDR Memory Transactions in High-Level Synthesis
Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…
Map Pattern in High-Level Synthesis
Data parallelism is mostly one of the first parallel execution patterns implemented in hardware and processor-based systems. In the simple…
Control Dependency in High-Level Synthesis
Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can…
Regular and Irregular Applications in HLS
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…
Make Your Design in Vitis a Winner
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…
How to Display an Image in Vitis Running on Ultra96v2 FPGA Embedded System
Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…
FPGA Platforms in Vitis
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…
FPGA in End-Devices/Edge/Cloud Computing
This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three…
Image Blending in High-Level Synthesis
The image blending operator combines two images of the same size to generate the third image. This blog post will…
Function Acceleration on FPGA with Vitis-Part 1: Fundamental
This online course is an introduction to function acceleration in high-level synthesis (HLS). The course's goals are to describe, debug…