Light Sensor Controller in HLS
This project aims to display the output of a light sensor on a seven-segment display in HLS. If you are…
How to Modify a C/C++ Program for HLS – 01
Compiling a software-implemented algorithm in HLS does not usually provide the performance expected from a hardware accelerator. Therefore, code modification…
“Logic System Design with High-Level Synthesis”: an Introductory Course for Undergraduate
This article introduces an introductory course on high-level synthesis (HLS) that is suitable for undergraduate students and software or hardware…
Reducing II in HLS: Partially-Unrolled Loop
Let’s consider the following code snippet. “High-Level Synthesis for FPGA” Online Courses The Xilinx Vitis-HLS synthesises the for-loop into a…
How to Emulate an FPGA Accelerator Using Xilinx Vitis
Designing and testing FPGA-based accelerators usually requires having access to expensive FPGA evaluation boards. Here, I will explain how we…
Logic Circuit Design with Xilinx Vitis-HLS
High-Level Synthesis increases the logic design abstraction level from RTL to the C-like high-level description. This higher abstraction level helps…