High-Level Synthesis increases the logic design abstraction level from RTL to the C-like high-level description.
This higher abstraction level helps designers focus on their logic systems or algorithms behaviour and protocols instead of spending lots of time converting them into a hardware description and then following the exhausting debugging processes.
The following figure shows the HLS-design flow. It consists of five stages.
1) The first stage is describing the given design or algorithm in HLS C/C++. Following a proper coding style is the key to develop an efficient digital system in HLS. The following online courses explain how to describe different designs and algorithms in HLS. They employ more than 200 quizzes and exercises to clarify all the aspects of code development in HLS. Three different design techniques are described in these courses:
- Single-cycle design flow
- Single-cycle Initiation Interval design flow
- Multi-cycle design flow
Online Courses:
– HIGH-LEVEL SYNTHESIS FOR FPGA, PART 1-COMBINATIONAL CIRCUITS
– HIGH-LEVEL SYNTHESIS FOR FPGA, PART 2 – SEQUENTIAL CIRCUITS
2) After describing our design in HLS, we can perform the C simulation. For this purpose, we should write a testbench in C/C++ and verify the design functionality. A testbench has its own coding style. The aforementioned online courses provide testbench code for all designs explained throughout the lessons. They also show that the C-simulation for a circuit described following the single-cycle design flow can provide cycle-accurate simulation.
3) After finishing the C-simulation, the high-level synthesis can be invoked. This process generates the corresponding RTL description. The synthesis report gives some metrics clarifying the design performance. The second course on sequential circuits in HLS explains some of the metrics and evaluates the design performance.
4) After finishing the synthesis process, the RTL/C co-simulation is enabled, which simulates the generated RTL design. This step uses the C testbench provided in the first stage. The output of the co-simulation can be shown in the Vivado waveform viewer.
5) Finally, we can generate the RTL IP to be used in a Vivado project.
The following video explains how to control an LED via the PMOD interface available on the Basys-3 board using the Xilinx Vitis-HLS toolset.