Reducing pipelined loops’ initiation-interval is the main goal of optimising an algorithm in HLS. Using conditional registers inside a pipelined-loop is one of the sources of high initiation-interval. Let’s consider the following function containing a pipelined for-loop. Note that all the defined variables used to keep data between loop iterations will be synthesised to registers in hardware if they survive the compiler optimisation passes. 

double conditional_register(double A[N], double B[N], int n) {


    double s = 0;

    for (int i = 0; i < n; i++) {
#pragma HLS PIPELINE
        double a = A[i] - B[i];
	if (a > 0)
	    s += a;
    return s;
}

In this code, the HLS tool synthesis the s variable into a register. The conditional statement encompassing the register modification prevents the synthesis tool from employing the pipeline optimisation efficiently. Therefore, the resulted II would be 6. The following figure shows the analysis perspective generated by using the Vitis-HLS 2020.2 toolset.

With a simple modification, this code can be synthesised into a pipelined microarchitecture with II=1. The idea is to change the conditional-register to a conditional-variable. The following code shows the modified code. In this code, the if-statement along with the t variable is synthesised into a simple multiplexer.

double conditional_register(double A[N], double B[N], int n) {


    double s = 0;

    for (int i = 0; i < n; i++) {
#pragma HLS PIPELINE
        double a = A[i] - B[i];
	double t;
	if (a > 0)
	    t = a;
	else
	    t = 0;
	s+=t;
    }
    return s;
}

The following figure shows the analysis perspective generated by using the Vitis-HLS 2020.2 toolset.

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