High-Level Synthesis for FPGA, Part 3 – Advanced
This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).
High-Level Synthesis for FPGA, Part 2 – Sequential Circuits
This course is an introduction to sequential circuit design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).
High-Level Synthesis for FPGA, Part 1-Combinational Circuits
This course is an elementary introduction to high-level synthesis (HLS) design flow. The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.
Function Acceleration on FPGA with Vitis-Part 1: Fundamental
This course is an introduction to function acceleration in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing compute-intensive algorithms on FPGA-based embedded systems using C/C++ language without any help from HDLs (e.g., VHDL or Verilog).
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