Generating digital waveform is one of the several basic tasks in the digital design area. Here I am going to write a straightforward C++ code in HLS to generate a waveform with a given 0 and 1 pattern.
In the “High-Level Synthesis for FPGA, Part 2-Sequential Circuits” course, I explained how to generate a waveform in HLS using a state machine; here, I am going to show an easier way to do so.
Let us assume the waveform pattern is 010001101; then, we should generate the following waveform.

The design has an output to generate the waveform and a few controlling input signals. The following code shows the hardware waveform generator design in HLS.
// 010001101 waveform pattern void waveform(volatile bool *a) { #pragma HLS INTERFACE mode=ap_none port=a #pragma HLS INTERFACE mode=ap_ctrl_hs port=return *a = 0; *a = 1; *a = 0; *a = 0; *a = 0; *a = 1; *a = 1; *a = 0; *a = 1; }
To test the design, we need a testbench which can be as follows.
void waveform(volatile bool *a); int main() { bool x; waveform(&x); waveform(&x); waveform(&x); waveform(&x); waveform(&x); waveform(&x); }
Now we should synthesise the code and perform the co-simulation and monitor the waveform in Vivado.
The following figure shows the result in Vivado waveform viewer.
