How can we control the execution of a hardware module generated by HLS flow? This post explains how to read the status of a module or command that to start its task.

Block-level interface protocols provide a mechanism for controlling the operation of an RTL module such that other modules and software applications can control the RTL module using the associated block-level interface.

By default, a block-level interface protocol is added to the design. The ports of a block-level interface

  • control when the block can start processing data (ap_start),
  • indicate when it is ready to accept new inputs (ap_ready),
  • and indicate if the design is idle (ap_idle) or has completed operation (ap_done).

Vitis HLS uses the following interface types to specify whether an RTL IP is implemented with block-level handshake signals.

  • ap_ctrl_none,
  • ap_ctrl_hs,
  • ap_ctrl_chain and
  • s_axilite

Block-level handshake signals specify the following:

  • When the design can start to perform the operation
  • When the operation ends
  • When the design is idle and ready for new inputs

You can specify the block-level I/O protocols on the function or the function return. If the C/C++ code does not return a value, you can still specify the block-level I/O protocol on the function return. If the C/C++ code uses a function return, Vitis HLS creates an output port ap_return for the return value.

The ap_ctrl_hs block-level I/O protocol is the default. The following figure shows the resulting RTL ports and behaviour when Vitis HLS implements ap_ctrl_hs on a function. In this example, the function returns a value using the return statement, and Vitis HLS creates the ap_return output port in the RTL design. If the function return statement is not included in the C/C++ code, this port is not created.

When the ap_rst signal is high, the module is in the reset state and cannot do anything. A low logic state on the ap_rst signal enables the module to accept the handshaking commands.

When the ap_start is received, the module puts the ap_idle signal to zero value indicating the design is no longer idle.

The module is performing its task and can receive input data or generate output data. When it finishes its task, the ap_done goes high, and the outputs are ready to be read by other modules or software.

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