Read/Write BRAM in HLS
This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…
AXI4 Memory Mapped I/O in HLS
This blog briefly explains the AXI4 Memory Mapped I/O protocol. The memory-mapped system is a common technique to access I/O…
One-Shot in HLS
A one-shot is a logic circuit with two states, of which only one is stable. This post explains how to…
Latency Measurement IP in HLS
This post explains how to write a simple HLS code to measure the latency of other IPs. The design will…
ZCU102 SW/HW Emulation Using Vitis-2022.2
This blog shows how to perform software and hardware emulations for ZCU102 platform using Vitis-2022.2. This flow has been tested…
Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform
The FPGA in the Kria KV260 board can be used to accelerate various software algorithms. The AMD-Xilinx Vitis toolset can…
How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1
In this blog, I will show how to emulate a software accelerator in Vitis 2022.1. I assume you have already…
Generating Waveform in HLS
Generating digital waveform is one of the several basic tasks in the digital design area. Here I am going to…
Block Level Interface Synthesis in HLS: ap_ctrl_hs
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…