Block Level Interface Synthesis in HLS: ap_ctrl_hs
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…
Mandelbrot Set in HLS
The Mandelbrot set is a group of complex numbers c for which the sequence number generated by the quadratic recurrence…
Hardware Synchronisation in HLS
Communication between two hardware modules is one of the main tasks in digital system design. When two tasks exchange signals…
DDR Memory Transactions in High-Level Synthesis
Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…
Map Pattern in High-Level Synthesis
Data parallelism is mostly one of the first parallel execution patterns implemented in hardware and processor-based systems. In the simple…
Control Dependency in High-Level Synthesis
Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can…
Regular and Irregular Applications in HLS
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…
Make Your Design in Vitis a Winner
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…
How to Display an Image in Vitis Running on Ultra96v2 FPGA Embedded System
Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…
FPGA Platforms in Vitis
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…