Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform
The FPGA in the Kria KV260 board can be used to accelerate various software algorithms. The AMD-Xilinx Vitis toolset can…
Kria KV260 and PetaLinux 2022.1: Part 01-Getting Started
This blog explains how to run PetaLinux 2022.1 on a Kria KV260 Vision AI Starter Kit.
How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1
In this blog, I will show how to emulate a software accelerator in Vitis 2022.1. I assume you have already…
Make Your Design in Vitis a Winner
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…
FPGA Platforms in Vitis
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…
Vitis 2021.1 Embedded Platform for Zybo-Z7-20
The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2
Creating the Ulra96v2 platform in the Xilinx Vitis 2020.2 has five steps: XSA design – Generating a Vivado project containing…
How to create Zybo-Z7-20 Vitis Hardware Accelerator Platform
Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental
Logic Circuit Design with Xilinx Vitis-HLS
High-Level Synthesis increases the logic design abstraction level from RTL to the C-like high-level description. This higher abstraction level helps…
Reducing II in HLS: Conditional Registers vs Conditional Variables
Reducing pipelined loops’ initiation-interval is the main goal of optimising an algorithm in HLS. Using conditional registers inside a pipelined-loop…