The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to learn high-level synthesis?”

The main goal of high-level synthesis in FPGA is accelerating applications. To understand the underlying concepts and design techniques, we should know how to use the available development tools.

The available development environments consist of two main parts: Software and Hardware.

Whereas the software part is responsible for synthesising a C/C++ code into its equivalent HDL code and then generating the FPGA bitstream and the compiled software codes, the hardware part is responsible for running the final application in the field.

Online Courses on HLS for FPGA

If you are interested in learning high-level synthesis for FPGA, please refer to my online course.

 Software

The Xilinx Vitis unified software platform consists of a few tools to develop and implement algorithms on FPGAs. The main goal of this software is to synthesis functions and algorithms described in C++ into their equivalent HDL code.

As shown in the following figure, the Xilinx Vitis design environment consists of four main tools. The top tool is called Vitis unified software platform, which calls three other tools to perform its subtasks. These tools include Vitis-HLS, Vivado and Vitis Analyser.

Vitis Unified Software Platform

For developing an application, we should create an application project in Vitis. The created Vitis project consists of three sub-projects. The first one is for the kernel code, and you should put the kernel source code under this project. The goal of this subproject is to perform the high-level synthesis and convert the C/C++ code into the equivalent RTL code.

The second project is based on the Xilinx Vivado synthesis tool and receives the generated RTL code and integrates that into the hardware platform. The goal of this project is to generate the bitstream of the hardware.

The third project contains the host code. The project uses gcc and g++ to compile the host to an executable file for the ARM processor that exists on the embedded system.

Finally, the Vitis project itself combines the FPGA bitstream and the executable host program into the target Linux platform and generates the SD Card files for booting the embedded system.

Vitis Projects

Online Courses on HLS for FPGA

If you are interested in learning high-level synthesis for FPGA, please refer to my online course.

Hardware

The Vitis toolset supports three groups of Xilinx FPGAs.

1- Zynq (MP)SoC platforms,

2- Versal™ adaptive compute acceleration platforms (ACAPs), and

3- UltraScale+™ architecture, including Alveo cards.

The first group includes FPGA based embedded systems that can be used for end-devices and edge computing.

The second group, ACAPs, are heterogeneous computing platforms. These platforms consist of three components: Scalar Engines, Adaptable Engines, and Intelligent Engines. They can be used for accelerating edge, cloud, and high-performance computing applications.

 The last group, Alveo cards, is designed for data centres and cloud computing (or mainly HPC).

The first group are cheap that is affordable for almost all designers and newbies. In addition, as they were the first platforms for which HLS was proposed, there are many resources, examples, and tutorials that newbies can access. The two other groups are relatively new and expensive, and all designers cannot afford them. Regarding the HLS design flow, you can almost learn the same design flow using an FPGA in one of these groups.

In summary, choosing the platform is depends on your applications and the underlying framework that you are going to run your applications, whether it is on end-devices, edge, or cloud. And for some embedded applications, Zynq & ZynqMPSoC are the best and only FPGA-based options.

Online Courses on HLS for FPGA

If you are interested in learning high-level synthesis for FPGA, please refer to my online course.

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