HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that their execution paths depend directly or indirectly on the input data. These applications usually use irregular memory access patterns to retrieve data from memory or save the results to the output data structures. Implementing these algorithms in HLS is a challenge and usually requires task-specific approaches.
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to learn high-level synthesis?”
This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three layers: End Devices, Edge (Fog) Platforms, and Cloud Computing.