Read/Write BRAM in HLS
This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…
AXI4 Memory Mapped I/O in HLS
This blog briefly explains the AXI4 Memory Mapped I/O protocol. The memory-mapped system is a common technique to access I/O…
Latency Measurement IP in HLS
This post explains how to write a simple HLS code to measure the latency of other IPs. The design will…
ZCU102 SW/HW Emulation Using Vitis-2022.2
This blog shows how to perform software and hardware emulations for ZCU102 platform using Vitis-2022.2. This flow has been tested…
How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1
In this blog, I will show how to emulate a software accelerator in Vitis 2022.1. I assume you have already…
Regular and Irregular Applications in HLS
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…
FPGA Platforms in Vitis
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…
FPGA in End-Devices/Edge/Cloud Computing
This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three…