High-Level Synthesis for FPGA: Online Courses
High-Level Synthesis for FPGA, Part 1-Combinational Circuits https://youtu.be/bgrUwNmuFq0 High-Level Synthesis for FPGA, Part 1-Combinational Circuits Special Offer: Link Daily Price:…
Generating Waveform in HLS
Generating digital waveform is one of the several basic tasks in the digital design area. Here I am going to…
Block Level Interface Synthesis in HLS: ap_ctrl_hs
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…
Mandelbrot Set in HLS
The Mandelbrot set is a group of complex numbers c for which the sequence number generated by the quadratic recurrence…
Hardware Synchronisation in HLS
Communication between two hardware modules is one of the main tasks in digital system design. When two tasks exchange signals…
DDR Memory Transactions in High-Level Synthesis
Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…
Map Pattern in High-Level Synthesis
Data parallelism is mostly one of the first parallel execution patterns implemented in hardware and processor-based systems. In the simple…
Control Dependency in High-Level Synthesis
Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can…
Regular and Irregular Applications in HLS
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…
Make Your Design in Vitis a Winner
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…