High-Level Synthesis for FPGA: Online Courses
High-Level Synthesis for FPGA, Part 1-Combinational Circuits https://youtu.be/bgrUwNmuFq0 High-Level Synthesis for FPGA, Part 1-Combinational Circuits Special Offer: Link Daily Price:…
ZCU102 SW/HW Emulation Using Vitis-2022.2
This blog shows how to perform software and hardware emulations for ZCU102 platform using Vitis-2022.2. This flow has been tested…
Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform
The FPGA in the Kria KV260 board can be used to accelerate various software algorithms. The AMD-Xilinx Vitis toolset can…
Kria KV260 and PetaLinux 2022.1: Part 01-Getting Started
This blog explains how to run PetaLinux 2022.1 on a Kria KV260 Vision AI Starter Kit.
How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1
In this blog, I will show how to emulate a software accelerator in Vitis 2022.1. I assume you have already…
Generating Waveform in HLS
Generating digital waveform is one of the several basic tasks in the digital design area. Here I am going to…
Block Level Interface Synthesis in HLS: ap_ctrl_hs
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…
Mandelbrot Set in HLS
The Mandelbrot set is a group of complex numbers c for which the sequence number generated by the quadratic recurrence…
Hardware Synchronisation in HLS
Communication between two hardware modules is one of the main tasks in digital system design. When two tasks exchange signals…
DDR Memory Transactions in High-Level Synthesis
Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…