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High-Level Synthesis & Embedded Systems

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Read/Write BRAM in HLS AXI4 Memory Mapped I/O in HLS One-Shot in HLS Latency Measurement IP in HLS ZCU102 SW/HW Emulation Using Vitis-2022.2
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FPGA-GPU-CPU Platform High-Level Synthesis Online Courses

High-Level Synthesis for FPGA: Online Courses

Mar 6, 2022 Mohammad

Hardware Design High-Level Synthesis

Read/Write BRAM in HLS

Apr 27, 2023 Mohammad

This post explains how to write to and read from a BRAM IP using HLS codes. I will write two…

FPGA-GPU-CPU Platform Hardware Design High-Level Synthesis

AXI4 Memory Mapped I/O in HLS

Apr 26, 2023 Mohammad

This blog briefly explains the AXI4 Memory Mapped I/O protocol. The memory-mapped system is a common technique to access I/O…

Hardware Design High-Level Synthesis

One-Shot in HLS

Apr 22, 2023 Mohammad

A one-shot is a logic circuit with two states, of which only one is stable. This post explains how to…

High-Level Synthesis

Latency Measurement IP in HLS

Apr 20, 2023 Mohammad

This post explains how to write a simple HLS code to measure the latency of other IPs. The design will…

Embedded System High-Level Synthesis

ZCU102 SW/HW Emulation Using Vitis-2022.2

Dec 19, 2022 Mohammad

This blog shows how to perform software and hardware emulations for ZCU102 platform using Vitis-2022.2. This flow has been tested…

Embedded System High-Level Synthesis

Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform

Jun 13, 2022 Mohammad

The FPGA in the Kria KV260 board can be used to accelerate various software algorithms. The AMD-Xilinx Vitis toolset can…

Embedded System

Kria KV260 and PetaLinux 2022.1: Part 01-Getting Started

Jun 12, 2022 Mohammad

This blog explains how to run PetaLinux 2022.1 on a Kria KV260 Vision AI Starter Kit.

Embedded System High-Level Synthesis

How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1

Jun 9, 2022 Mohammad

In this blog, I will show how to emulate a software accelerator in Vitis 2022.1. I assume you have already…

High-Level Synthesis

Generating Waveform in HLS

Dec 14, 2021 Mohammad

Generating digital waveform is one of the several basic tasks in the digital design area. Here I am going to…

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Online Course

High-Level Synthesis for FPGA, Part 3 – Advanced

Online Course

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

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Online Course

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

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Online Course

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

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You missed

Hardware Design High-Level Synthesis

Read/Write BRAM in HLS

Apr 27, 2023 Mohammad
FPGA-GPU-CPU Platform Hardware Design High-Level Synthesis

AXI4 Memory Mapped I/O in HLS

Apr 26, 2023 Mohammad
Hardware Design High-Level Synthesis

One-Shot in HLS

Apr 22, 2023 Mohammad
High-Level Synthesis

Latency Measurement IP in HLS

Apr 20, 2023 Mohammad

High-Level Synthesis & Embedded Systems

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