Embedded System, Hardware Design, High-Level Synthesis
High-Level Synthesis for FPGA: Online Courses
Embedded System, FPGA-GPU-CPU Platform, Hardware Design, High-Level Synthesis, OpenCL
Support Vector Machine on Zynq (Zybo-Z7-20)
Embedded System, FPGA-GPU-CPU Platform, Hardware Design, OpenCL
Vitis 2021.1 Embedded Platform for Zybo-Z7-20
Embedded System, Hardware Design, High-Level Synthesis, OpenCL
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2
Embedded System, FPGA-GPU-CPU Platform, High-Level Synthesis, OpenCL
How to create Zybo-Z7-20 Vitis Hardware Accelerator Platform
Impact of Loop Index Data Type on Performance
How to Reduce II in HLS: Part 4
How to Reduce II in HLS: Part 3
How to Use Ultra96v2 to Control Four LEDs.
Reducing II in HLS – 002 (Conditional Histogram Kernel)
