How to Display an Image in Vitis Running on Ultra96v2 FPGA Embedded System
Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…
FPGA Platforms in Vitis
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…
FPGA in End-Devices/Edge/Cloud Computing
This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three…
Image Blending in High-Level Synthesis
The image blending operator combines two images of the same size to generate the third image. This blog post will…
Function Acceleration on FPGA with Vitis-Part 1: Fundamental
This online course is an introduction to function acceleration in high-level synthesis (HLS). The course's goals are to describe, debug…
High-Level Synthesis for FPGA, Part 2 – Sequential Circuits
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…
High-Level Synthesis for FPGA, Part 1-Combinational Circuits
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…
Support Vector Machine on Zynq (Zybo-Z7-20)
This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board. The Xilinx Vitis…
Vitis 2021.1 Embedded Platform for Zybo-Z7-20
The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2
Creating the Ulra96v2 platform in the Xilinx Vitis 2020.2 has five steps: XSA design – Generating a Vivado project containing…