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High-Level Synthesis & Embedded Systems

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High-Level Synthesis for FPGA: Online Courses Generating Waveform in HLS Block Level Interface Synthesis in HLS: ap_ctrl_hs Mandelbrot Set in HLS Hardware Synchronisation in HLS
High-Level Synthesis

How to Display an Image in Vitis Running on Ultra96v2 FPGA Embedded System

Oct 10, 2021 Mohammad

Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…

Embedded System High-Level Synthesis

FPGA Platforms in Vitis

Oct 9, 2021 Mohammad

The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…

High-Level Synthesis

FPGA in End-Devices/Edge/Cloud Computing

Oct 7, 2021 Mohammad

This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three…

High-Level Synthesis

Image Blending in High-Level Synthesis

Oct 6, 2021 Mohammad

The image blending operator combines two images of the same size to generate the third image. This blog post will…

Online Courses

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Oct 3, 2021 Mohammad

This online course is an introduction to function acceleration in high-level synthesis (HLS). The course's goals are to describe, debug…

Online Courses

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Oct 3, 2021 Mohammad

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…

Online Courses

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Oct 3, 2021 Mohammad

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…

High-Level Synthesis

Support Vector Machine on Zynq (Zybo-Z7-20)

Aug 23, 2021 Mohammad

This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board. The Xilinx Vitis…

Embedded System

Vitis 2021.1 Embedded Platform for Zybo-Z7-20

Aug 15, 2021 Mohammad

The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.…

Embedded System

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2

Aug 14, 2021 Mohammad

Creating the Ulra96v2 platform in the Xilinx Vitis 2020.2 has five steps: XSA design – Generating a Vivado project containing…

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Online Course

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Exceptional Offer: Link

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Uncategorized

High-Level Synthesis for FPGA: Online Courses

Mar 6, 2022 Mohammad
High-Level Synthesis

Generating Waveform in HLS

Dec 14, 2021 Mohammad
High-Level Synthesis

Block Level Interface Synthesis in HLS: ap_ctrl_hs

Nov 29, 2021 Mohammad
High-Level Synthesis

Mandelbrot Set in HLS

Nov 28, 2021 Mohammad

High-Level Synthesis & Embedded Systems

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