Skip to content
Thu. Sep 28th, 2023

High-Level Synthesis & Embedded Systems

  • Home
  • About
  • Contact
Top Tags
  • High-Level Synthesis
  • FPGA
  • Vitis platform
  • Edge Computing
  • Basys3
  • Online Courses on HLS
  • Zynq

Latest Post

Read/Write BRAM in HLS AXI4 Memory Mapped I/O in HLS One-Shot in HLS Latency Measurement IP in HLS ZCU102 SW/HW Emulation Using Vitis-2022.2
Search
High-Level Synthesis

Block Level Interface Synthesis in HLS: ap_ctrl_hs

Nov 29, 2021 Mohammad

How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…

High-Level Synthesis

Mandelbrot Set in HLS

Nov 28, 2021 Mohammad

The Mandelbrot set is a group of complex numbers c for which the sequence number generated by the quadratic recurrence…

High-Level Synthesis

Hardware Synchronisation in HLS

Nov 22, 2021 Mohammad

Communication between two hardware modules is one of the main tasks in digital system design. When two tasks exchange signals…

High-Level Synthesis

DDR Memory Transactions in High-Level Synthesis

Oct 25, 2021 Mohammad

Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…

High-Level Synthesis

Map Pattern in High-Level Synthesis

Oct 23, 2021 Mohammad

Data parallelism is mostly one of the first parallel execution patterns implemented in hardware and processor-based systems. In the simple…

High-Level Synthesis

Control Dependency in High-Level Synthesis

Oct 22, 2021 Mohammad

Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can…

High-Level Synthesis

Regular and Irregular Applications in HLS

Oct 21, 2021 Mohammad

HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…

Embedded System High-Level Synthesis

Make Your Design in Vitis a Winner

Oct 19, 2021 Mohammad

The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…

High-Level Synthesis

How to Display an Image in Vitis Running on Ultra96v2 FPGA Embedded System

Oct 10, 2021 Mohammad

Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…

Embedded System High-Level Synthesis

FPGA Platforms in Vitis

Oct 9, 2021 Mohammad

The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…

Posts navigation

1 2 3 … 9
Subscribe to Blog via Email

Enter your email address to subscribe to this blog and receive notifications of new posts by email.

Online Course

High-Level Synthesis for FPGA, Part 3 – Advanced

Online Course

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Exceptional Offer: Link

You missed

Hardware Design High-Level Synthesis

Read/Write BRAM in HLS

Apr 27, 2023 Mohammad
FPGA-GPU-CPU Platform Hardware Design High-Level Synthesis

AXI4 Memory Mapped I/O in HLS

Apr 26, 2023 Mohammad
Hardware Design High-Level Synthesis

One-Shot in HLS

Apr 22, 2023 Mohammad
High-Level Synthesis

Latency Measurement IP in HLS

Apr 20, 2023 Mohammad

High-Level Synthesis & Embedded Systems

  • Home
  • Activity
  • Dynamic Energy Management in Zynq SoC
  • How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2
  • About
  • Contact

All High-Level Synthesis for FPGA Courses

Special Offer
X
 

Loading Comments...