Block Level Interface Synthesis in HLS: ap_ctrl_hs
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…
How can we control the execution of a hardware module generated by HLS flow? This post explains how to read…
The Mandelbrot set is a group of complex numbers c for which the sequence number generated by the quadratic recurrence…
Communication between two hardware modules is one of the main tasks in digital system design. When two tasks exchange signals…
Communicating with DDR memories in FPGA can be a performance bottleneck for FPGA accelerators. Using a proper data transaction protocol…
Data parallelism is mostly one of the first parallel execution patterns implemented in hardware and processor-based systems. In the simple…
Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can…
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that…
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure…
Display an image is one of the common tasks in embedded system applications, including applications running on embedded FPGA systems…
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to…