Control Dependency in High-Level Synthesis

Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can help programmers to develop an efficient application.

Parallelism means running different operations or tasks simultaneously, which can be done using separate or shared resources. The HLS tools can provide parallelism by mapping the concurrency in a design code description onto hardware resources. 

Concurrency means the ability to execute different blocks of a code simultaneously, which does not necessarily mean at the same time. Dependencies among code modules are the primary source for studying and exploiting concurrency in a program.

Dependency represents the interaction among code modules. There are two types of dependency between every two modules (or statements): data dependency and control dependency. Data dependency defines the data production-consumption relationship between two modules. The control dependency determines that a module or statement can prevent the execution of another module or statement.

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Control Dependency

There is a control dependency between two statements when one of them controls the execution of the other. In HLS, a control dependency can change the structure of the target hardware and degrade the efficiency of exposing concurrency in a code. For example, in the following code, the if-condition at Line 3 controls the statement’s execution at Line 4.

...
if (a > 0)
	s = b+c;
...

The value of s should be updated if a  is greater than zero; otherwise, the previous value of a should be preserved. The following figure shows the corresponding RTL design after synthesising this code. As can be seen, it consists of a multiplexer and a register to save the value of s. This coding style introduces a loop carried dependency if the if-statement is used in a pipelined for-loop statement, which may cause a high initiation interval and reduce the performance.

RTL structure of if-statement code dependency without else

If the HLS tool can infer the previous value of s, as shown in the code below, then the corresponding RTL code does not require any register to save the s variable. As can be seen, the resulting RTL structure is a combinational circuit that doesn’t infer any carried dependencies if the if-statement is used in a pipelined for-loop.

...
s = 0;
if (a > 0)
	s = b+c;
...
RTL structure of if-statement code dependency with else

Summary

Choosing a proper coding style to reduce the control dependency in an HLS code can directly improve the final design performance.

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If you are interested in learning high-level synthesis for FPGA, please refer to my online course.

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