Dependency, concurrency and parallelism are three main concepts in high-level synthesis code development. A proper understanding of these concepts can help programmers to develop an efficient application. Hence, this chapter explains their differences and relationships.
HLS tools are able to parallelise regular tasks on FPGAs efficiently. However, some applications show a dynamic behaviour such that their execution paths depend directly or indirectly on the input data. These applications usually use irregular memory access patterns to retrieve data from memory or save the results to the output data structures. Implementing these algorithms in HLS is a challenge and usually requires task-specific approaches.
The final project in my online course has recently won the September Project Hero prize in the Big Xcellent Adventure with Xilinx. Here I briefly explain the key technique to develop such a project.
The goal of this post is to answer this question: “Which Vitis FPGA platform is more suitable for newbies to learn high-level synthesis?”
This blog aims to explain the role of FPGA and high-level synthesis in the new computing architecture comprises of three layers: End Devices, Edge (Fog) Platforms, and Cloud Computing.
The image blending operator combines two images of the same size to generate the third image. This blog post will explain how to describe this operator in HLS using the Xilinx Vitis unified software platform.
This online course is an introduction to function acceleration in high-level synthesis (HLS). The course’s goals are to describe, debug and implement compute-intensive algorithms on FPGA-based embedded systems using Xilinx Vitis Toolsets.
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course’s goals are to describe, debug and implement sequential logic circuits on FPGAs using Xilinx Vivado+Vitis-HLS Toolsets.
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course’s goals are to describe, debug and implement combinational logic circuits on FPGAs using Xilinx Vivado+Vitis-HLS Toolsets.
This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board. The Xilinx Vitis unified software platform is used …
