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High-Level Synthesis & Embedded Systems

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ZCU102 SW/HW Emulation Using Vitis-2022.2 Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform Kria KV260 and PetaLinux 2022.1: Part 01-Getting Started How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1 High-Level Synthesis for FPGA: Online Courses
Online Courses

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Oct 3, 2021 Mohammad

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…

High-Level Synthesis

Support Vector Machine on Zynq (Zybo-Z7-20)

Aug 23, 2021 Mohammad

This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board. The Xilinx Vitis…

Embedded System

Vitis 2021.1 Embedded Platform for Zybo-Z7-20

Aug 15, 2021 Mohammad

The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.…

Embedded System

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2

Aug 14, 2021 Mohammad

Creating the Ulra96v2 platform in the Xilinx Vitis 2020.2 has five steps: XSA design – Generating a Vivado project containing…

Embedded System

How to create Zybo-Z7-20 Vitis Hardware Accelerator Platform

Aug 13, 2021 Mohammad

Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental

High-Level Synthesis

Impact of Loop Index Data Type on Performance

Jun 1, 2021 Mohammad

Loop index can have a great impact on the accelerator performance described in HLS.Here, using an example, I am going…

High-Level Synthesis

How to Reduce II in HLS: Part 4

May 24, 2021 Mohammad

This week’s problem is the traditional matrix-vector multiplication kernel used in several applications such as machine learning and image processing.…

How to Reduce II in HLS: Part 3

May 17, 2021 Mohammad

This week problem is one of the benchmarks presented in the Cheng paper. BNNKernel is a small binarised neural network……

How to Use Ultra96v2 to Control Four LEDs.

May 9, 2021 Mohammad

Reducing II in HLS – 002 (Conditional Histogram Kernel)

May 4, 2021 Mohammad

The conditional histogram kernel, described by the following code, is used as a benchmark to evaluate several dynamic schedulers and…

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Online Course

High-Level Synthesis for FPGA, Part 3 – Advanced

Online Course

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Exceptional Offer: Link

You missed

Embedded System High-Level Synthesis

ZCU102 SW/HW Emulation Using Vitis-2022.2

Dec 19, 2022 Mohammad
Embedded System High-Level Synthesis

Kria KV260 and PetaLinux 2022.1: Part 02- Vitis Platform

Jun 13, 2022 Mohammad
Embedded System

Kria KV260 and PetaLinux 2022.1: Part 01-Getting Started

Jun 12, 2022 Mohammad
Embedded System High-Level Synthesis

How to Emulate an Hardware Accelerator on ZCU102 in Vitis 2022.1

Jun 9, 2022 Mohammad

High-Level Synthesis & Embedded Systems

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High-Level Synthesis for FPGA, Part 3 - Advanced

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