High-Level Synthesis for FPGA, Part 1-Combinational Circuits
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The course's goals are to describe, debug…
Support Vector Machine on Zynq (Zybo-Z7-20)
This project aims to implement the Support Vector Machine (SVM) on a Zynq 7000 or Zynq-MPSoC board. The Xilinx Vitis…
Vitis 2021.1 Embedded Platform for Zybo-Z7-20
The goal of this blog is to create a Vitis 2021.1 hardware accelerator platform for the Zybo-Z7-20 board from Digilent.…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.2
Creating the Ulra96v2 platform in the Xilinx Vitis 2020.2 has five steps: XSA design – Generating a Vivado project containing…
How to create Zybo-Z7-20 Vitis Hardware Accelerator Platform
Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental Udemy Course: Function Acceleration on FPGA with Vitis-Part 1: Fundamental
Impact of Loop Index Data Type on Performance
Loop index can have a great impact on the accelerator performance described in HLS.Here, using an example, I am going…
How to Reduce II in HLS: Part 4
This week’s problem is the traditional matrix-vector multiplication kernel used in several applications such as machine learning and image processing.…
How to Reduce II in HLS: Part 3
This week problem is one of the benchmarks presented in the Cheng paper. BNNKernel is a small binarised neural network……
Reducing II in HLS – 002 (Conditional Histogram Kernel)
The conditional histogram kernel, described by the following code, is used as a benchmark to evaluate several dynamic schedulers and…