Reducing II in HLS: Conditional Registers vs Conditional Variables
Reducing pipelined loops’ initiation-interval is the main goal of optimising an algorithm in HLS. Using conditional registers inside a pipelined-loop…
SCII Design Approach in HLS
SCII design approach is introduced in the “High-Level Synthesis for FPGA” course for the first time. “High-Level Synthesis for FPGA…
Stepper Motor Controller in High-Level Synthesis
The goal of this mini-project is to drive a 4-phase bipolar stepper motor using high-level synthesis for FPGA. To achieve…
Reducing II in HLS: Loop Interchange
Abstract: This blog shows how the loop interchange optimisation technique in HLS can improve the design performance. If you would…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Bandwidth Optimisation
Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster.
A four-digit up/down counter on BASYS-3 FPGA Board Using Vitis-2020.1
The goal of this design is very similar to that of this post. Here, we are going to have a…
Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model
In this model, an application code is divided into two parts: host code and kernels. Kernels are the tasks that…
UART Transmit with HLS for FPGA
UART is an old mechanism for serial communication which still is used in several electronic boards and computing platforms. Its…
Digital Clock in HLS
The goal of this project is to demonstrate the capability of HLS in designing digital systems. For this purpose, I…
Digital Dice Roller in HLS
Abstract: Designing digital systems with HLS is fun and easy. In this project, I am going to implement a digital…