SCII design approach is introduced in the “High-Level Synthesis for FPGA” course for the first time.  “High-Level Synthesis for FPGA Part 2” is a course that takes the Diligent Basys3 FPGA board and the Xilinx Vitis-HLS toolset to explain how to describe a logic circuit efficiently in HLS.

Using High-Level Synthesis (HLS) to design logic circuits is one of the key skills that future hardware engineers should have. Although HLS has increased the level of abstraction to describe hardware modules, there are a few coding styles and skills that still should be learned before efficiently coding hardware modules.

Udemy course: “High-Level Synthesis for FPGA, Part 2 – Sequential Circuits”, Logic Design with Vitis-HLS

The SCII design approach combines the single-cycle design flow and the function pipelining with the initiation interval of one to provide a systematic approach to design logic circuits.  

The concept of function pipelining in HLS and the corresponding initiation interval is explained in the course employing several examples. This idea is used to expand the single-cycle design flow into SCII (single-cycle initiation interval). The course illustrates how a logic circuit can be described in HLS  using the SCII design flow. The final circuit can accept inputs in every clock cycle without missing any inputs.

The single-cycle design flow assumes that the combinational part of a sequential circuit takes only one clock cycle to perform its tasks and generates the next state and the circuit outputs.

Several logic circuits fulfil this single cycle constraint. The course proposes HLS coding styles and techniques to employ this single-cycle design concept to design logic circuits and controllers.

The course describes how to design a wide range of logic circuits in HLS, including timers, counters, pulse generators, controller systems, data exchange protocols

The course starts with explaining the D-flip-flop as the simplest memory cell.

Then it introduces the design clock frequency concept in HLS and its role in describing circuits.

After that, the course explains the idea of single-cycle design and its benefits.

Then, it generalises the single-cycle design flow with the SCII design concept.

Finally, it introduces the multi-cycle design concept in HLS and how to use port interfaces to implement this concept.

In addition, the course explains

  • How to write a testbench
  • How to perform C-Simulation and Debugging
  • How to perform RTL/C Co-simulation and debugging
  • How to perform run-time debugging using ILA IP

In summary, the course proposes two main techniques to design logic circuits:

SCII design flow and multi-cycle design flow.

Udemy course: “High-Level Synthesis for FPGA, Part 2 – Sequential Circuits”, Logic Design with Vitis-HLS