A four-digit up/down counter on BASYS-3 FPGA Board Using Vitis-2020.1
The goal of this design is very similar to that of this post. Here, we are going to have a…
Running Ubuntu 18.04 on Ultra96v2 Using Petalinux 2019.2, with Networking
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Preparing Ubuntu 18.04 for running on Ultra96v2 has five sections…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Ports
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course In this blog, I am going to explain…
Embedded Hardware Accelerator with Xilinx Vitis: Part 2: Create a Linux-based Platform
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course In the previous blog in this series, I…
Fundamentals of High-Level Synthesis Part 3: From Concurrency to Parallelism (Map Pattern)
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course In the previous blog, I explained the difference between…
Fundamentals of High-Level Synthesis Part 2: Concurrency vs Parallelism
Concurrency and parallelism are two main concepts in high-level synthesis (HLS) design flow that their understanding is crucial in implementing…
Fundamentals of High-Level Synthesis Part 1: Basic Concepts
With the emergence of compute-intensive applications in different areas such as Artificial Intelligence (AI), Machine Learning (ML), Convolutional Neural Networks…
Embedded Hardware Accelerator with Xilinx Vitis: Part 1: Concept of Platform
Goal: FPGA-based accelerator design flow is at the stage that software engineers can benefit from without an in-depth knowledge of…
Convolutional Neural-Network on Zynq –part 00: Convolution in Caffe
Recently, I have started to used FPGA (e.g. Zynq) to run neural-networks (NNs) defined in Caffe. My first step is…
Runtime System Energy Management on Xilinx Zynq
Runtime system is a group of function running a separate thread than the application to monitor and manage the energy…