This article introduces an introductory course on high-level synthesis (HLS) that is suitable for undergraduate students and software or hardware designers with minimum logic design knowledge. The course covers the design of all traditional circuits explained in an HDL-based logic system design course. Currently the course has two parts that contain 17 hours on-demand videos and more than 300 downloadable resources including quizzes, exercises solutions and their source and testbench codes in HLS. For accessing the course series please refer here.
High-level synthesis (HLS) is becoming a must-have skill for FPGA-based embedded system designers. Several industrial and academic tools are available that synthesise an algorithm described in a high-level language such as C/C++. This shows that HLS tools can convert a C code into the corresponding logic design. However, there is no systematic design methodology to describe a logic circuit in HLS. Whereas HDL languages such as VHDL and Verilog have been accepted as the industrial standard for describing logic systems, the HLS is not used widely by the industry as the description language for logic systems. There are several reasons for that
1- The hardware resulted from HLS is not efficient
2- There is not any systematic methodology that describes all types of logic systems.
3- There is no undergraduate course that specifically explains the logic design in HLS.
4- Low-level hardware debugging in HLS is not possible
I have designed a series of courses on logic design in HLS that addresses these reasons. The main target students of these courses are undergraduate students who know the very fundamental concepts in logic circuits.
The first aforementioned reason is just a myth, as the current HLS tools can synthesis C codes into hardware that can perform meaningful tasks in each clock cycle. Therefore, the resulted hardware can be as fast as the counterpart descriptions in HDLs. In these courses, I have shown how to implement high-performance logic circuits in HLS, such that the final hardware can utilise every clock cycle and provide maximum throughput.
These courses also propose systematic design techniques for all classical logic circuits including, combinatorial circuits, sequential circuits and state machines. They propose two main design methodologies: single-cycle and multi-cycle.
The combinational part of the logic circuit in the single-cycle design methodology takes only one clock cycle to finish. This means the circuit is ready to accept inputs and generate outputs in every clock cycle.
However, some circuits may take more than one clock cycle to finish. In this case, the HLS generates multi-cycle hardware. This type of circuits may not consume input data or generate output data in each clock cycle.
The course explains how function pipelining can be used to improve the multi-cycle design performance and throughout. If the initiation interval of the pipelined function is one, then the corresponding circuit can receive input data or generate output data in each clock cycle. The behaviour of a pipelined multi-cycle design with an initiation interval of 1 is very similar to a single-cycle design. Therefore, the course gives a unique name to these two design approaches: Single-Cycle Initiation Interval or SCII (pronounce ski) design approach.
These courses also propose how to use handshaking mechanisms and data streaming to implement efficient multi-cycle designs.
The course is designed for undergraduate students with very basic logic design knowledge. It contains several quizzes, exercises, and projects to evaluate their understandings and master the proposed techniques.
Three different debugging mechanisms are explained to evaluate the designs, including C-simulation, RTL/C co-simulation, and runtime waveform monitoring using ILA IP. These debugging approaches guide designers to evaluate the functionality, cycle accuracy, and timing of the circuit under design.