Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1

Creating the Ulra96v2 platform in the Xilinx Vitis has four steps:

  1. XSA design – Generating a Vivado project containing the underlying hardware
  2. Linux OS – Generating a PetaLinux project to configure Linux
  3. Create Platform – Using Xilinx Vitis to generate the Platform
  4. Test– Create a simple application to test the generated platform

In the sequel, I am trying to briefly explain each step. I have installed Xilinx Vitis and Petalinux 2019.2 under the Ubuntu 18.04 OS. Note that, the Xilinx Vitis software includes Vivado, so you do not need to install that separately.

To make Vivado detects the board, copy the Avnet ultra96v2 board definition files (at here) to the <Vivado installation folder>/data/boards/board_files.

1- XSA design

1- create a directory called ultra96v2-vitis-pkg

mkdir ultra96v2-vitis-pkg
cd ultra96v2-vitis-pkg/

2- create a director called vivado

mkdir vivado 
cd vivado

3- Run Vivado and create a project called ultra96v2-xsa in the ultra96v2-vitis-pkg/vivado folder. Figures 1-6 show the flow of the project creation.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6

4- In the Vivado project, create a block design with the name of ultra96v2_design.

Figure 7

5- Add a Zynq UltraScale+ MPSoC IP into the Diagram view

Figure 8

6- Click on “Run Block Automation” and make sure “Apply Board Reset” is selected.

Figure 9

7- Double click on the Zynq IP and configure that as Figure 10

Figure 10

8- Add a Clocking Wizard IP to the design.

Figure 11

9- Double click on the added IP and configure that as Figure 12. Add four output clocks with different output frequencies, and make sure that the reset type is “Active Low”.

Figure 12

10- Add four Processor System Reset IPs corresponding to the four output clocks.

Figure 13

11- Add connections as Figure 14.

Figure 14

12- Add a Concat IP

Figure 15

13- Configure the added IP as Figure 16 and connect that to the Zynq as shown in Figure 7.

Figure 16
Figure 17

14- Now, we should declare the platform (PFM) interface and properties. For this purpose, select “Platform Interfaces” option from the “Window” menu in the Vivado IDE. (Window–>Platform Interfaces).

15- Click on “Enable platform interfaces” if this the first time you select the Platform Interfaces option in the project.

16- Right-click on each option and select Enable to enable the following interfaces:

M_AXI_HPM0_FPD
M_AXI_HPM1_FPD
M_AXI_HPM0_LPD
S_AXI_HPC0_FPD
S_AXI_HPC1_FPD
S_AXI_HP0_FPD
S_AXI_HP1_FPD
S_AXI_HP2_FPD
S_AXI_HP3_FPD
17- Select S_AXI_HPC0_FPD port and write HPC0 in the sptag under Option in Platform Interface Properties pannel. For other ports do similar setting
S_AXI_HPC0_FPD ---> HPC0
S_AXI_HPC1_FPD ---> HPC1
S_AXI_HP0_FPD ---> HP0
S_AXI_HP1_FPD ---> HP1
S_AXI_HP2_FPD ---> HP2
S_AXI_HP3_FPD ---> HP3

Note, to change the sptag filed you must press the Enter key on your keyboard. So, don't forget to press Enter each time.

18- Enable the following clock interfaces

clk_out1
clk_out2
clk_out3
clk_out4

19- Select the enabled clk_out1 and in the Options window change the id to 0 and select the is_default. Note, to change the id filed you must press the Enter key on your keyboard. Change ids of clk_out2, clk_out3, and clk_out4 to 1, 2, and 3, respectively.

20- In the xlconcat_0 interfaces, enable In0, Int1, Int2, Int3, Int4, Int5, Int6, Int7, which are interrupt interfaces.

21- Go to the “TCL Console” view and run these commands

set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]

22- Press the right-click in Diagram view and in the popup menu select Validate Design.

23- Press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Generate Output Products…”.

24- Select the Generate button and wait for the process to finish.

25- Again, press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Create HDL Wrapper… ” and select the “Let Viviado manage wrapper and auto-update” option in the dialog box.

26- Then under the PROGRAM AND DEBUG option in the left-hand side panel, select “Generate Bitstream” and wait until the end of the process.

27- After generating the bitstream, go to the TCL Console view and make sure you are in the right folder. you can use pwd command to check the folder. Go to “ultra96v2-vitis-pkg/vivado” that you have created. and run the following TCL command to generate the XSA file

write_hw_platform -include_bit ultra96v2.xsa

28- You can validate the generated XSA file by running the following TCL command.

validate_hw_platform ./ultra96v2.xsa

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

2- Linux OS

1- Go to the “ultra96v2-vitis-pkg” folder generated in the first step (i.e., 1-XSA design) and run the followoing commands

mkdir linux_files
mkdir  linux_files/boot

2- Run the setting.sh file located at the PetaLinux installation folder by running this command

source /home/opt/petalinux/2019.2/settings.sh

3- In the “ultra96v2-vitis-pkg” folder create a PetaLinux project

petalinux-create -t project --template zynqMP -n ultra96v2-petalinux

4- Go to the generated project folder and configure the project

cd ultra96v2-petalinux
petalinux-config --get-hw-description=../vivado

5- In the “misc/config System Configuration” window, go to “Subsystem AUTO Hardware Settings–>Serial Setting” and change the “psu_uart_0” to “psu_uart_1” and back to the main menu.

5- In the “DTG Settings –>Kernel Bootargs–>” disable generate boot args automatically” option. then in the “user set kernel bootargs” enter the following arguments

earlycon clk_ignore_unused root=/dev/ram rw

6- Save and exit the configuration window.

7- The next step is kernel configuration using the following command

petalinux-config -c kernel

8- In the “Linux/arm64 4.19.0 Kernel Configuration” window, go to “Device Drivers–>Generic Driver Options–>Size in Mega bytes” and change 256 to 1024

9- Save and exit the kernel configuration window

10- Edit the file “./project-spec/meta-user/conf/user-rootfsconfig” and add the following lines

CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv

11- Open the “./project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi” file and modify that as follows.

/include/ "system-conf.dtsi"
 / {
    amba {
      mmc@ff160000 {
        u-boot,dm-pre-reloc;
        compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
        status = "okay";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x30 0x4>;
        reg = <0x0 0xff160000 0x0 0x1000>;
        clock-names = "clk_xin", "clk_ahb";
        xlnx,device_id = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0xd 0x870>;
        power-domains = <0xc 0x27>;
        clocks = <0x3 0x36 0x3 0x1f>;
        clock-frequency = <0xb2d0529>;
        xlnx,mio_bank = <0x0>;
        no-1-8-v;
        disable-wp;
      };
    };
 };
&amba {
   zyxclmm_drm {
     compatible = "xlnx,zocl";
     status = "okay";
     reg = <0x0 0xA0000000 0x0 0x10000>;
   };
 };

12- Configure the linux rootfs by running the following command

petalinux-config -c rootfs

13- Go to the “user packages” menu and select the following packages

opencl-hpp-dev
opencl-headers-dev
packagegroup-petalinux-opencv
xrt
xrt-dev
zocl

14- Then build the peralinux project by running this command.

petalinux-build

15- The go to images/linux folder

cd images/linux

and run this command

petalinux-build --sdk

16- Then run the ./sdk.sh command and enter the full path of the linux_files folder that you created at the first phase.

17- Copy the following files from the image/linux folder into the linux_files/boot folder that you created in the first phase.

image.ub
zynqmp_fsbl.elf
pmufw.elf
bl31.elf
u-boot.elf

18- In the linux_files/boot folder create the linux.bif file containing the following lines

/* linux */
the_ROM_image:
{
  [fsbl_config] a53_x64
  [bootloader] <zynqmp_fsbl.elf>
  [pmufw_image] <pmufw.elf>
  [destination_device=pl] <bitstream> 
  [destination_cpu=a53-0, exception_level=el-3, trustzone] <bl31.elf>
  [destination_cpu=a53-0, exception_level=el-2] <u-boot.elf>
}

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

3- Create Platform

1- Create a folder named pfm in the ultra96v2-vitis-pkg folder that you created in the first step.

cd pfm

To create the ultra96v2 platform for Vitis. First, run the Vitis IDE and choose the pfm folder (that you created in the first step) as the workspace.

2- Create a new platform project by selecting “File–>New–>Platform Project…”. Choos “ultra96v2” as the project name and accept the default folder.

3- In the next window select the XSA option and press Next

4- Click on Brows… button and locate the ultra96v2.xsa file generated in the first step by Vivado, and then select the linux as Operating System and click Finish button.

5- Clock the Welcome window if it is open. Select “linux on psu_cortexa53” and configure the Linux domain as the following figure.

6- Press the right-click on the project name on the left panel and select Build Project.

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

4- Test

1- In the Vitis IDE, select “File–>New–>Application Project…” to create a new application.

2- Select vector_add as the Project name

3- Select the ultra96v2 [custom] platform in the next window

4- Press the Next button in the next window.

5- Select the Vector Addition as the template and press Finish button.

6- Select Hardware as the active build configuration from the menu on the right.

7- Build the project by pressing the right-click on the project name and selecting the Build project option.

8- Copy the content of the sd_card folder generated by the application project into an SD-CARD and boot the U;tra96v2 board.

9- Using putty open a serial terminal with the following configuration

10- login to the board by using root as both username and password. Then go to /run/media/mmcblk0p1 folder

11- Run the following commands to define the Xilinx XRT library

export XILINX_XRT=/usr

12- Run the application by running this command

./vector_add.exe binary_container_1.xclbin

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits