Embedded Hardware Accelerator with Xilinx Vitis: Part 3: Programming Model
In this model, an application code is divided into two parts: host code and kernels. Kernels are the tasks that…
UART Transmit with HLS for FPGA
UART is an old mechanism for serial communication which still is used in several electronic boards and computing platforms. Its…
Digital Clock in HLS
The goal of this project is to demonstrate the capability of HLS in designing digital systems. For this purpose, I…
Digital Dice Roller in HLS
Abstract: Designing digital systems with HLS is fun and easy. In this project, I am going to implement a digital…
Floating-Point Numbers on 7-Segment Display in HLS
Abstract: In this small project I am going to show a floating-point number on 4-digit seven-segments using HLS. If you…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Creating the Ulra96v2 platform in the Xilinx Vitis 2020.1 has…
A 0-9 Up/Down Counter in HLS
Goal: The main goal of this project is demonstrating the power and capability of high-level synthesis design flow in implementing…
The Importance of Combinational Circuits in HLS
Abstract: Describing a combinational task in HLS is very important as it has a direct impact on the whole system…
Embedded Hardware Accelerator with Xilinx Vitis: Part 4: Ports
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course In this blog, I am going to explain…
Fundamentals of High-Level Synthesis – Part 4: Dependency, Concurrency and parallelism
In the last two blogs, I explicitly talked about concurrency and parallelism. I also explained the dependency. However, the dependency…