Embedded Hardware Accelerator with Xilinx Vitis: Part 1: Concept of Platform
FPGA-based accelerator design flow is at the stage that software engineers can benefit from without an in-depth knowledge of hardware…
How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1 Creating…
How to Install pocl on Jetson TX1
Installation: Download and install llvm+clang from http://releases.llvm.org/6.0.0/clang+llvm-6.0.0-aarch64-linux-gnu.tar.xz Download and install hwloc v1.0 or newer from https://www.open-mpi.org/software/hwloc/v1.0/ Download and install ocl-icd from…
Sparse Matrix-Vector Multiplication (SpMV) on Zynq FPGA
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Reference for this blog: M. Hosseinabady and J. L. Nunez-Yanez,…
Runtime System Energy Management on Xilinx Zynq
Runtime system is a group of function running a separate thread than the application to monitor and manage the energy…
Energy Modeling on Xilinx Zynq
A group of Matlab functions create a regression model for the FPGA tasks using the power monitoring data obtained by…
Design Benchmarks on Zynq
A group of tasks implemented by Vivado-HLS for Zynq are available at here. For comparison their performance also their software…
Frequency Scaling on Xilinx Zynq
Goal Frequency scaling on Zynq FPGA Approach Write to the divider registers in the Zynq Benefits Changing the FPGA frequency Credit…
Voltage Scaling on Xilinx Zynq
Goal Voltage scaling on Zynq Approach Using PMBus protocol to change the value on voltage rails Benefits Power and energey…
Voltage Monitoring on Zynq
Goal Monitoring power consumption on Zynq Approach Reading voltage, current and power on different voltage rails on Zynq Benefits Getting…