Mohammad | Goal | Frequency scaling on Zynq FPGA |
| Approach | Write to the divider registers in the Zynq |
| Benefits | Changing the FPGA frequency |
| Credit | This work has been done under the ENPOWER project (funded by EPSRC) at University of Bristol. |
The power monitoring library contains a few functions to change the PL or PS frequencies.
To change the PL frequency the following function can be used
u32 pl_frequency_set(int pl_clock, int divisor0, int divisor1);
in which pl_clock variable denote one of the controllable clock frequency in the PL whose value can be
FPGA0_CLK, FPGA1_CLK, FPGA2_CLK and FPGA3_CLK
The frequency on the FPGA is determined by 1000/(divisor0*divisor1) MHz.
Example:
#include "set_frequency.h"
#include <string.h>
int main(int argc, char *argv[]) {
int divisor0;
int divisor1;
if (argc == 3) {
divisor0 = atoi(argv[1]);
divisor1 = atoi(argv[2]);
printf("new frequency is 1000/(%d*%d) = %f\n", divisor0, divisor1, 1000.0/(divisor0*divisor1));
} else {
printf("The command had no other arguments.\n");
return -1;
}
pl_frequency_set(FPGA0_CLK, divisor0, divisor1);
pl_frequency_set(FPGA1_CLK, divisor0, divisor1);
pl_frequency_set(FPGA2_CLK, divisor0, divisor1);
pl_frequency_set(FPGA3_CLK, divisor0, divisor1);
}
The monitoring library can be found at here.
sir it is possible without linux if possible to provide some material