High-Level Synthesis for FPGA Online Courses

This design consists of an 8-bit up counter with a configurable delay (through signal called delay) and activating signal called run.

The run signal is connected to the EMIO GPIO(0) and delay is connected to PS through AXI Lite which can be controlled in software.

The output of the counter is shown on DS15, DS16, DS17, DS18, DS19, DS20, DS21 and DS22 LEDs available on ZC702 board.

The following figure shows this counter.

The following code shows the synthesizable C++ code for this counter

[code language="c"]
typedef unsigned char u8;

void enpower_pl_counter(volatile bool run, volatile int delay, volatile u8 *counter) {
#pragma HLS INTERFACE ap_none register port=counter
#pragma HLS INTERFACE ap_none register port=delay
#pragma HLS INTERFACE ap_none register port=run
#pragma HLS RESOURCE variable=delay  core=AXI4LiteS metadata="-bus_bundle CONTROL_BUS"
#pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle CONTROL_BUS"

  volatile u8 counter_reg = 0;

  while(run == 1) {
    volatile int i = 0;
    for (i = 0; i < delay; i++);
    *counter = counter_reg++;
  }
}
[/code]

The Vivado design is as follows

High-Level Synthesis for FPGA Online Courses

The following c code shows how to use this design in standalone environment

#include "stdio.h"
#include "xenpower_pl_counter.h"

#define GPIO_BASE 0xE000A000

#define MASK_DATA_2_LSW (GPIO_BASE+0x00000010)
#define DIRM_2 (GPIO_BASE+0x00000284)
#define OEN_2 (GPIO_BASE+0x00000288)

XEnpower_pl_counter counter;

int main()
{
int status;

print("Hello World\n\r");

XEnpower_pl_counter_Config *CfgPtr;
CfgPtr = XEnpower_pl_counter_LookupConfig(XPAR_ENPOWER_PL_COUNTER_0_DEVICE_ID);
if(!CfgPtr){
print("Error looking for AXI Device config\n\r");
return XST_FAILURE;
}

status = XEnpower_pl_counter_CfgInitialize(&counter,CfgPtr);
if(status != XST_SUCCESS){
print("Error initializing Device\n\r");
return XST_FAILURE;
}

u32 delayValue = 0x000FFFFF;
XEnpower_pl_counter_SetDelay(&counter, delayValue);
XEnpower_pl_counter_Start(&counter);

u32 drim_value = *(volatile u32 *)DIRM_2;
drim_value = drim_value | 0x00000001;
*(volatile u32 *)DIRM_2 = drim_value;

drim_value = *(volatile u32 *)OEN_2;
drim_value = drim_value | 0x00000001;
*(volatile u32 *)OEN_2 = drim_value;

*(volatile u32 *) MASK_DATA_2_LSW = 0xFFFE0001;

return 0;
}
}

High-Level Synthesis for FPGA Online Courses