Random Number Generator in HLS Using LFSR

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

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Linear Feedback Shift Register (LFSR) is a shift register that can be used to generate random numbers in hardware.

The following code represents an LFSR with equation x^{32}+x^{22}+x^2+x+1

unsigned int pseudo_random(unsigned int seed, int load) {
  static ap_uint<32> lfsr;
  if (load ==1 )
    lfsr = seed;
  bool b_32 = lfsr.get_bit(32-32);
  bool b_22 = lfsr.get_bit(32-22);
  bool b_2 = lfsr.get_bit(32-2);
  bool b_1 = lfsr.get_bit(32-1);
  bool new_bit = b_32 ^ b_22 ^ b_2 ^ b_1;
  lfsr = lfsr >> 1;
  lfsr.set_bit(31, new_bit);

  return lfsr.to_uint();

}

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

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12 Comments

  1. Can anyone tell what would be the result for Random number Generator. I have tried vivado HLS, but i am not getting proper result. So, please share code for Random binary sequence Generator.

    1. if you run the code with the following testbench you will get these numbers

      rand = 2147483663, 1073741831, 536870915, 2415919105, 1207959552, 2751463424, 3523215360, 1761607680, 3028287488, 3661627392, 1830813696,

      printf (“rand = %u, “, pseudo_random(31, 1)); //load&use the LFSR
      for (int i = 0; i < 10; i++) {
      unsigned int r = pseudo_random(31, 0); //use the LFSR
      printf ("%u, ", r);
      }

      1. Thanks for your response. Currently, i am working with Pseudo_random binary sequence (0`s & 1’s).

        I want to call it repeatedly and get a different bit of the lfsr sequence, Ineed to define the “lfsr” variable as static and do only one step of the lfsr update each time it’s called. So get rid of the do while loop in PRBS_prj, declare lfsr as static and update lfsr just once per call of the accelerated function. How it is possible ? Please correct my code

        HLS Source code

        #include
        #include
        #include “ap_cint.h”

        int PRBS_prj()
        {
        #pragma HLS INTERFACE s_axilite port=return bundle=a
        int start_state = 0xCD;
        int lfsr = start_state;
        bool bit;
        unsigned period = 0;

        do
        {
        /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */
        bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1;
        printf(“%d”, bit);
        lfsr = (lfsr >> 1) | (bit << 7);
        ++period;
        } while (lfsr != start_state);
        return bit;
        }

  2. As your polynomial is of degree 3 the LFSR has 3 bits and 2^3-1=7 states. The following code can generate random binary values of length 7.

    bool pseudo_random() {
    	static ap_uint<3> lfsr=5;
    
    	//x^3 + x^2 + 1
    	bool b_3 = lfsr.get_bit(3-3);
    	bool b_2 = lfsr.get_bit(3-2);
    
    	bool new_bit = b_3 ^ b_2 ;
    	lfsr = lfsr &gt;&gt; 1;
    	lfsr.set_bit(2, new_bit);
    
    	return lfsr.get_bit(0);
    
    }
    
    1. Thanks for your response. Currently I’m working with Kintex 7 and micorblaze, for Pseudo-random bit sequence function. I have executed PRBS in HLS and created HLS IP , then integrated HLS IP with vivado, generated bit stream and exported it to SDK.

      Actually, I need to return Pseudo_random bit sequences like 0`s and 1`s into XSDK through HLS IP.

      But in SDK, i am getting only “Single bit” value (either 0 or 1) instead of sequence of random bits while dumping into hardware. Any idea about that problem. ! If anyone, Please guide me.

      1. If you want a non-stop stream of random bits out of the IP, then one way is using FIFO for connecting the IP to PS and hls::stream at the output of the HLS code.
        For steam data communication between an IP and SDK you can have a look at the Xilinx examples or other resources on the web .

  3. Hi, I have tried with using FIFO for steam data communication between an IP and SDK. But still i am unable to get steam data at UART (Tera Terminal)., getting onley single bit either 0 or 1. Please suggest and help. I am stucking with this project nearly 15 days.

    HLS Source code

    int PRBS2(unsigned int *b)
    {

    #pragma HLS INTERFACE s_axilite port=b bundle=a

    static unsigned lfsr = 0xCD;
    int i,j;
    int bit;
    unsigned int arr[50];

    for ( i = 0; i > 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1;
    arr[i] = bit;
    b=arr;
    lfsr = (lfsr >> 1) | (bit << 7);
    }
    for (j = 0; j < 50; j++)
    {
    printf("%d", *b);
    b++;
    }
    return 0;
    }

  4. Can anyone share the idea of how to generate Pseudo_Random Number pattern In Vivado HLS? for example Pattern like 6,32,64,128,256,512,1024,2048,5096. I have tried with your HLS code, but i am not getting Random Number pattern. In Hls, Printf is not accepted then how. Please share your logic ?

    1. Use this code snippet in a main function and simulet the pseudo_random function, then you will get the random pattern.

      printf (“rand = %u, “, pseudo_random(31, 1)); //load&use the LFSR
      for (int i = 0; i < 10; i++) {
      unsigned int r = pseudo_random(31, 0); //use the LFSR
      printf ("%u, ", r);
      }
      

      change the feedback polynomial in pseudo_random for generating your own random pattern.

      1. You talking about test bench. But i need to execute synthesis process in VIVADO. In your code printf statement is their, but in hls printf statement is not accepted then how can i execute. Please suggest me.

      2. add interfaces to the code as you need in your vivado then generate the corresponding IP using the Vivado-HLS and use the generated IP in the vivado.
        for more details and examples please refer to xilinx tutorials such as “UG871 – Vivado Design Suite Tutorial High-Level Synthesis”

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