Goal Reducing II in a pipelined loop
Approach Balanced if
Benefits Faster design using High-level Synthesis
Credit

Let’s consider this code

#define N 2014
int reduce_freq(float a[N], float b[N], float c[N]) {
    for (unsigned int i = 0; i < N; i++) {
#pragma HLS PIPELINE
        c[i] += a[i]*b[i];
        if (i == 0 ) {
            c[i] += a[i];
        }
    }
    return 0;
}

After synthesising this code with the target period of 10 nsec for Zynq, the estimated period is 9.97, the initiation interval (II) is 12 and iteration latency is 24.

By converting the if condition in the code into an balanced if condition with two parts (i.e., if and else) and transfer the computation outside the condition into the if block, the II reduces to 6 which can lead to 50% improvement in throughput. Also, the iteration latency becomes 18 which less than 24.

Therefore, balanced if can improve the latency and throughput in a pipelined for loop.

This is the code

#define N 2014
int reduce_freq(float a[N], float b[N], float c[N]) {
    for (unsigned int i = 0; i < N; i++) {
#pragma HLS PIPELINE

        if (i == 0 ) {
            c[i] += a[i] + a[i]*b[i];
        } else {
            c[i] += a[i]*b[i];
        }
    }
    return 0;
}