Skip to content
Thu. Sep 28th, 2023

High-Level Synthesis & Embedded Systems

  • Home
  • About
  • Contact
Top Tags
  • High-Level Synthesis
  • FPGA
  • Vitis platform
  • Edge Computing
  • Basys3
  • Online Courses on HLS
  • Zynq

Latest Post

Read/Write BRAM in HLS AXI4 Memory Mapped I/O in HLS One-Shot in HLS Latency Measurement IP in HLS ZCU102 SW/HW Emulation Using Vitis-2022.2
Search
Embedded System Software

Large Matrix-Matrix Multiplication on Dual-Core Cortex-A9+NEON

Nov 24, 2016 Mohammad

Goal Fast Matrix-Matrix Multiplication on Software Approach Cache-friendly code, using dual-core (with OpenMP) and NEON vector processor Benefits Very fast Matrix-Matrix…

Hardware Design High-Level Synthesis OpenCL

Vector Addition in FPGA OpenCL: Part 1

Nov 23, 2016 Mohammad

Goal Implementing a large vector-addition on FPGA Approach Stream computing Benefits Utilising high memory bandwidth Credit  This work has been…

Hardware Design High-Level Synthesis

Reducing II in HLS: Balanced-Paths

Nov 23, 2016 Mohammad

the goal of this blog is to show the impact of unbalanced conditional paths in high-level synthesis. For this purpose,…

Hardware Design High-Level Synthesis OpenCL

Covariance: An OpenCL Implementation on Xilinx FPGA-Part 1

Nov 1, 2016 Mohammad

Goal Implementing the Covariance application for Xilinx FPGA Approach OpenCL for SDAccel Benefits Learning how to describe an application in…

Embedded System FPGA-GPU-CPU Platform Hardware Design

How to compile Xilinx Linux Kernel for zynq

Oct 31, 2016 Mohammad

High-Level Synthesis for FPGA Online Courses Goal Compile Xilinx Linux kernel to be run on Zynq along with the Ubuntu…

Hardware Design High-Level Synthesis

How to run an OpenCL Code on Xilinx FPGA using NIMBIX Cloud

Oct 25, 2016 Mohammad

Goal Run an OpenCL program on Xilinx FPGA Approach Using SDAccel to compile and NIMBIX Cloud to run the program…

Embedded System Hardware Design High-Level Synthesis

Large Matrix-Matrix Multiplication on FPGA

Oct 1, 2016 Mohammad

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Goal Implementing a large matrix-matrix multiplication on FPGA Approach Using…

Posts navigation

1 … 8 9
Subscribe to Blog via Email

Enter your email address to subscribe to this blog and receive notifications of new posts by email.

Online Course

High-Level Synthesis for FPGA, Part 3 – Advanced

Online Course

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Exceptional Offer: Link

Online Course

High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Exceptional Offer: Link

You missed

Hardware Design High-Level Synthesis

Read/Write BRAM in HLS

Apr 27, 2023 Mohammad
FPGA-GPU-CPU Platform Hardware Design High-Level Synthesis

AXI4 Memory Mapped I/O in HLS

Apr 26, 2023 Mohammad
Hardware Design High-Level Synthesis

One-Shot in HLS

Apr 22, 2023 Mohammad
High-Level Synthesis

Latency Measurement IP in HLS

Apr 20, 2023 Mohammad

High-Level Synthesis & Embedded Systems

  • Home
  • Activity
  • Dynamic Energy Management in Zynq SoC
  • How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2
  • About
  • Contact

All High-Level Synthesis for FPGA Courses

Special Offer
X
 

Loading Comments...