Random Number Generator in HLS Using LFSR
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Udemy Course  Linear Feedback Shift Register (LFSR) is a…
Designing an 8-bit counter using Vivado-HLS for Zynq
High-Level Synthesis for FPGA Online Courses This design consists of an 8-bit up counter with a configurable delay (through signal…
Large Matrix-Matrix Multiplication on Dual-Core Cortex-A9+NEON
Goal Fast Matrix-Matrix Multiplication on Software Approach Cache-friendly code, using dual-core (with OpenMP) and NEON vector processor Benefits Very fast Matrix-Matrix…
Vector Addition in FPGA OpenCL: Part 1
Goal Implementing a large vector-addition on FPGA Approach Stream computing Benefits Utilising high memory bandwidth Credit This work has been…
Reducing II in HLS: Balanced-Paths
the goal of this blog is to show the impact of unbalanced conditional paths in high-level synthesis. For this purpose,…
Covariance: An OpenCL Implementation on Xilinx FPGA-Part 1
Goal Implementing the Covariance application for Xilinx FPGA Approach OpenCL for SDAccel Benefits Learning how to describe an application in…
How to compile Xilinx Linux Kernel for zynq
High-Level Synthesis for FPGA Online Courses Goal Compile Xilinx Linux kernel to be run on Zynq along with the Ubuntu…
How to run an OpenCL Code on Xilinx FPGA using NIMBIX Cloud
Goal Run an OpenCL program on Xilinx FPGA Approach Using SDAccel to compile and NIMBIX Cloud to run the program…
Large Matrix-Matrix Multiplication on FPGA
Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits Goal Implementing a large matrix-matrix multiplication on FPGA Approach Using…