High-Level Synthesis for FPGA, Part 1-Combinational Circuits
Exceptional Offer: Link
High-Level Synthesis for FPGA, Part 2-Sequential Circuits
Exceptional Offer: Link
Function Acceleration on FPGA with Vitis-Part 1: Fundamental (Embedded System Accelerators)
Exceptional Offer: Link
[…] If you are interested in using Vitis to accelerate applications on Zynq, please refer to here or here. […]
[…] High-Level Synthesis for FPGA: Online Courses […]
[…] If you are interested in learning high-level synthesis for FPGA, please refer to my online course. […]
[…] If you are interested in learning high-level synthesis for FPGA, please refer to my online course. […]
[…] If you are interested in learning high-level synthesis for FPGA, please refer to my online course. […]
[…] Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits […]
[…] If you are interested in function acceleration in HLS, please refer to here. […]
[…] In the previous blog, I explained how to implement the image thresholding example in Vitis for ZynqMPSOC. Here, I am going to optimise the kernel and reduce the execution time and make the hardware about 13x faster. If you would like to learn how to code hardware in HLS please refer here. […]