How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2020.1

Creating the Ulra96v2 platform in the Xilinx Vitis has four steps:

  1. XSA design – Generating a Vivado project containing the underlying hardware
  2. Linux OS – Generating a PetaLinux project to configure Linux
  3. Create Platform – Using Xilinx Vitis to generate the Platform
  4. Test– Create a simple application to test the generated platform

In the sequel, I am trying to briefly explain each step. I have installed Xilinx Vitis and Petalinux 2019.2 under the Ubuntu 18.04 OS. Note that, the Xilinx Vitis software includes Vivado, so you do not need to install that separately.

To make Vivado detects the board, copy the Avnet ultra96v2 board definition files (at here) to the <Vivado installation folder>/data/boards/board_files.

1- XSA design

1- create a directory called ultra96v2-vitis-pkg

mkdir ultra96v2-vitis-pkg
cd ultra96v2-vitis-pkg/

2- create a director called vivado

mkdir vivado 
cd vivado

3- Run Vivado and create a project called ultra96v2-xsa in the ultra96v2-vitis-pkg/vivado folder. Figures 1-6 show the flow of the project creation.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6

4- In the Vivado project, create a block design with the name of ultra96v2_design.

Figure 7

5- Add a Zynq UltraScale+ MPSoC IP into the Diagram view

Figure 8

6- Click on “Run Block Automation” and make sure “Apply Board Reset” is selected.

Figure 9

7- Double click on the Zynq IP and configure that as Figure 10

Figure 10

8- Add a Clocking Wizard IP to the design.

Figure 11

9- Double click on the added IP and configure that as Figure 12. Add four output clocks with different output frequencies, and make sure that the reset type is “Active Low”.

Figure 12

10- Add four Processor System Reset IPs corresponding to the four output clocks.

Figure 13

11- Add connections as Figure 14.

Figure 14

12- Add a Concat IP

Figure 15

13- Configure the added IP as Figure 16 and connect that to the Zynq as shown in Figure 7.

Figure 16
Figure 17

14- Now, we should declare the platform (PFM) interface and properties. For this purpose, select “Platform Interfaces” option from the “Window” menu in the Vivado IDE. (Window–>Platform Interfaces).

15- Click on “Enable platform interfaces” if this the first time you select the Platform Interfaces option in the project.

16- Right-click on each option and select Enable to enable the following interfaces:

M_AXI_HPM0_FPD
M_AXI_HPM1_FPD
M_AXI_HPM0_LPD
S_AXI_HPC0_FPD
S_AXI_HPC1_FPD
S_AXI_HP0_FPD
S_AXI_HP1_FPD
S_AXI_HP2_FPD
S_AXI_HP3_FPD
17- Select S_AXI_HPC0_FPD port and write HPC0 in the sptag under Option in Platform Interface Properties pannel. For other ports do similar setting
S_AXI_HPC0_FPD ---> HPC0
S_AXI_HPC1_FPD ---> HPC1
S_AXI_HP0_FPD ---> HP0
S_AXI_HP1_FPD ---> HP1
S_AXI_HP2_FPD ---> HP2
S_AXI_HP3_FPD ---> HP3

Note, to change the sptag filed you must press the Enter key on your keyboard. So, don't forget to press Enter each time.

18- Enable the following clock interfaces

clk_out1
clk_out2
clk_out3
clk_out4

19- Select the enabled clk_out1 and in the Options window change the id to 0 and select the is_default. Note, to change the id filed you must press the Enter key on your keyboard. Change ids of clk_out2, clk_out3, and clk_out4 to 1, 2, and 3, respectively.

20- In the xlconcat_0 interfaces, enable In0, Int1, Int2, Int3, Int4, Int5, Int6, Int7, which are interrupt interfaces.

21- Go to the “TCL Console” view and run these commands

set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]

22- Press the right-click in Diagram view and in the popup menu select Validate Design.

23- Press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Generate Output Products…”.

24- Select the Generate button and wait for the process to finish.

25- Again, press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Create HDL Wrapper… ” and select the “Let Viviado manage wrapper and auto-update” option in the dialog box.

26- Then under the PROGRAM AND DEBUG option in the left-hand side panel, select “Generate Bitstream” and wait until the end of the process.

27- After generating the bitstream, go to the TCL Console view and make sure you are in the right folder. you can use pwd command to check the folder. Go to “ultra96v2-vitis-pkg/vivado” that you have created. and run the following TCL command to generate the XSA file

write_hw_platform -include_bit ultra96v2.xsa

28- You can validate the generated XSA file by running the following TCL command.

validate_hw_platform ./ultra96v2.xsa

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

2- Linux OS

1- Go to the “ultra96v2-vitis-pkg” folder generated in the first step (i.e., 1-XSA design) and run the followoing commands

mkdir linux_files
mkdir  linux_files/boot

2- Run the setting.sh file located at the PetaLinux installation folder by running this command

source /home/opt/petalinux/2019.2/settings.sh

3- In the “ultra96v2-vitis-pkg” folder create a PetaLinux project

petalinux-create -t project --template zynqMP -n ultra96v2-petalinux

4- Go to the generated project folder and configure the project

cd ultra96v2-petalinux
petalinux-config --get-hw-description=../vivado

5- In the “misc/config System Configuration” window, go to “Subsystem AUTO Hardware Settings–>Serial Setting” and change the “psu_uart_0” to “psu_uart_1” and back to the main menu.

5- In the “DTG Settings –>Kernel Bootargs–>” disable generate boot args automatically” option. then in the “user set kernel bootargs” enter the following arguments

earlycon clk_ignore_unused root=/dev/ram rw

6- Save and exit the configuration window.

7- The next step is kernel configuration using the following command

petalinux-config -c kernel

8- In the “Linux/arm64 4.19.0 Kernel Configuration” window, go to “Device Drivers–>Generic Driver Options–>Size in Mega bytes” and change 256 to 1024

9- Save and exit the kernel configuration window

10- Edit the file “./project-spec/meta-user/conf/user-rootfsconfig” and add the following lines

CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv

11- Open the “./project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi” file and modify that as follows.

/include/ "system-conf.dtsi"
 / {
    amba {
      mmc@ff160000 {
        u-boot,dm-pre-reloc;
        compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
        status = "okay";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x30 0x4>;
        reg = <0x0 0xff160000 0x0 0x1000>;
        clock-names = "clk_xin", "clk_ahb";
        xlnx,device_id = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0xd 0x870>;
        power-domains = <0xc 0x27>;
        clocks = <0x3 0x36 0x3 0x1f>;
        clock-frequency = <0xb2d0529>;
        xlnx,mio_bank = <0x0>;
        no-1-8-v;
        disable-wp;
      };
    };
 };
&amba {
   zyxclmm_drm {
     compatible = "xlnx,zocl";
     status = "okay";
     reg = <0x0 0xA0000000 0x0 0x10000>;
   };
 };

12- Configure the linux rootfs by running the following command

petalinux-config -c rootfs

13- Go to the “user packages” menu and select the following packages

opencl-hpp-dev
opencl-headers-dev
packagegroup-petalinux-opencv
xrt
xrt-dev
zocl

14- Then build the peralinux project by running this command.

petalinux-build

15- The go to images/linux folder

cd images/linux

and run this command

petalinux-build --sdk

16- Then run the ./sdk.sh command and enter the full path of the linux_files folder that you created at the first phase.

17- Copy the following files from the image/linux folder into the linux_files/boot folder that you created in the first phase.

image.ub
zynqmp_fsbl.elf
pmufw.elf
bl31.elf
u-boot.elf

18- In the linux_files/boot folder create the linux.bif file containing the following lines

/* linux */
the_ROM_image:
{
  [fsbl_config] a53_x64
  [bootloader] <zynqmp_fsbl.elf>
  [pmufw_image] <pmufw.elf>
  [destination_device=pl] <bitstream> 
  [destination_cpu=a53-0, exception_level=el-3, trustzone] <bl31.elf>
  [destination_cpu=a53-0, exception_level=el-2] <u-boot.elf>
}

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

3- Create Platform

1- Create a folder named pfm in the ultra96v2-vitis-pkg folder that you created in the first step.

cd pfm

To create the ultra96v2 platform for Vitis. First, run the Vitis IDE and choose the pfm folder (that you created in the first step) as the workspace.

2- Create a new platform project by selecting “File–>New–>Platform Project…”. Choos “ultra96v2” as the project name and accept the default folder.

3- In the next window select the XSA option and press Next

4- Click on Brows… button and locate the ultra96v2.xsa file generated in the first step by Vivado, and then select the linux as Operating System and click Finish button.

5- Clock the Welcome window if it is open. Select “linux on psu_cortexa53” and configure the Linux domain as the following figure.

6- Press the right-click on the project name on the left panel and select Build Project.

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

4- Test

1- In the Vitis IDE, select “File–>New–>Application Project…” to create a new application.

2- Select vector_add as the Project name

3- Select the ultra96v2 [custom] platform in the next window

4- Press the Next button in the next window.

5- Select the Vector Addition as the template and press Finish button.

6- Select Hardware as the active build configuration from the menu on the right.

7- Build the project by pressing the right-click on the project name and selecting the Build project option.

8- Copy the content of the sd_card folder generated by the application project into an SD-CARD and boot the U;tra96v2 board.

9- Using putty open a serial terminal with the following configuration

10- login to the board by using root as both username and password. Then go to /run/media/mmcblk0p1 folder

11- Run the following commands to define the Xilinx XRT library

export XILINX_XRT=/usr

12- Run the application by running this command

./vector_add.exe binary_container_1.xclbin

Digital System Design with High-Level Synthesis for FPGA: Combinational Circuits

How to create Ultra96v2 Linux-based Platform in Xilinx Vitis 2019.2

Creating the Ulra96v2 platform in the Xilinx Vitis has four steps:

  1. XSA design – Generating a Vivado project containing the underlying hardware
  2. Linux OS – Generating a PetaLinux project to configure Linux
  3. Create Platform – Using Xilinx Vitis to generate the Platform
  4. Test– Create a simple application to test the generated platform

In the sequel, I am trying to briefly explain each step. I have installed Xilinx Vitis and Petalinux 2019.2 under the Ubuntu 18.04 OS. Note that, the Xilinx Vitis software includes Vivado, so you do not need to install that separately.

To make Vivado detects the board, copy the Avnet ultra96v2 board definition files (at here) to the <Vivado installation folder>/data/boards/board_files.

1- XSA design

1- create a directory called ultra96v2-vitis-pkg
mkdir ultra96v2-vitis-pkg
cd ultra96v2-vitis-pkg/

2- create a director called vivado
mkdir vivado
cd vivado

3- Run Vivado and create a project called ultra96v2-xsa in the ultra96v2-vitis-pkg/vivado folder. Figures 1-6 show the flow of the project creation.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6

4- In the Vivado project, create a block design with the name ultra96v2_design.

Figure 7

5- Add a Zynq UltraScale+ MPSoC IP into the Diagram view

Figure 8

6- Click on “Run Block Automation” and make sure the “Apply Board Reset” is selected.

Figure 9

7- Double click on the Zynq IP and configure that as Figure ???

Figure 10

8- Add a Clocking Wizard IP to the design.

Figure 11

9- Double click on the added IP and configure that as Figure 12. Add four output clocks and make sure that the reset type is “Active Low”.

Figure 12

10- Add four Processor System Reset IPs corresponding to four output clocks.

Figure 13

11- Add connections as Figure 14.

Figure 14

12- Add a Concat IP

Figure 15

13- Configure the added IP as Figure 16 and connect that to the Zynq as shown in Figure 7.

Figure 16
Figure 17

14- Now, we should declare the platform (PFM) interface and properties. For this purpose, select “Platform Interfaces” option from the “Window” menu in the Vivado IDE. (Window–>Platform Interfaces).

15- Click on “Enable platform interfaces” if this the first time you select the Platform Interfaces option in the project.

16- By write click on each option and select Enable to enable the following interfaces:

M_AXI_HPM0_FPD
M_AXI_HPM1_FPD
M_AXI_HPM0_LPD
S_AXI_HPC0_FPD
S_AXI_HPC1_FPD
S_AXI_HP0_FPD
S_AXI_HP1_FPD
S_AXI_HP2_FPD
S_AXI_HP3_FPD

17- Enable the following clock interfaces

clk_out1
clk_out2
clk_out3
clk_out4

18- Select the enabled clk_out1 and in the Options window change the id to 0 and select the is_default. Note, to change the id filed you must press the Enter key on your keyboard. Change ids of clk_out2, clk_out3, and clk_out4 to 1, 2, and 3, respectively.

19- In the xlconcat_0 interfaces, enable In0, Int1, Int2, Int3, Int4, Int5, Int6, Int7, which are interrupt interfaces.

20- Go to the “TCL Console” view and run these commands

set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type “sd_card” [current_project]

21- Press the right-click in Diagram view and in the popup menu select Validate Design.

22- Press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Generate Output Products…”.

23- Select the Generate button and wait for the process to finish.

24- Again, press the right-click on the “ultra96v2_design (ultra96v2_design.bd)” option in the source view panel. And from the popup menu select “Create HDL Wrapper… ” and select the “Let Viviado manage wrapper and auto-update” option in the dialog box.

25- Then under the PROGRAM AND DEBUG option in the left-hand side panel, select “Generate Bitstream” and wait until the end of the process.

25- After generating the bitstream, go to the TCL Console view and make sure you are in the right folder. you can use pwd command to check the folder. Go to “ultra96v2-vitis-pkg/vivado” that you have created. and run the following TCL command to generate the XSA file

write_hw_platform -include_bit ultra96v2.xsa

26- You can validate the generated XSA file by running the following TCL command.

validate_hw_platform ./ultra96v2.xsa

2- Linux OS

1- Go to the “ultra96v2-vitis-pkg” folder generated in the first step (i.e., 1-XSA design) and run the followoing commands

mkdir linux_files
mkdir linux_files/boot

2- Run the setting.sh file located at the PetaLinux installation folder by running this command

source /home/opt/petalinux/2019.2/settings.sh

3- In the “ultra96v2-vitis-pkg” folder create a PetaLinux project

petalinux-create -t project –template zynqMP -n ultra96v2-petalinux

4- Go to the generated project folder and configure the project

cd ultra96v2-petalinux
petalinux-config –get-hw-description=../vivado

5- In the “misc/config System Configuration” window, go to “Subsystem AUTO Hardware Settings–>Serial Setting” and change the “psu_uart_0” to “psu_uart_1” and back to the main menu.

5- In the “DTG Settings –>Kernel Bootargs–>” disable generate boot args automatically” option. then in the “user set kernel bootargs” enter the following arguments

earlycon clk_ignore_unused root=/dev/ram rw

6- Save and exit the configuration window.

7- The next step is kernel configuration using the following command

petalinux-config -c kernel

8- In the “Linux/arm64 4.19.0 Kernel Configuration” window, go to “Device Drivers–>Generic Driver Options–>Size in Mega bytes” and change 256 to 1024

9- Save and exit the kernel configuration window

10- Edit the file “./project-spec/meta-user/conf/user-rootfsconfig” and add the following lines

CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv

11- Open the “./project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi” file and modify that as follows.

/include/ “system-conf.dtsi”
/ {
amba {
mmc@ff160000 {
u-boot,dm-pre-reloc;
compatible = “xlnx,zynqmp-8.9a”, “arasan,sdhci-8.9a”;
status = “okay”;
interrupt-parent = <0x4>;
interrupts = <0x0 0x30 0x4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = “clk_xin”, “clk_ahb”;
xlnx,device_id = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0xd 0x870>;
power-domains = <0xc 0x27>;
clocks = <0x3 0x36 0x3 0x1f>;
clock-frequency = <0xb2d0529>;
xlnx,mio_bank = <0x0>;
no-1-8-v;
disable-wp;
};
};
};
&amba {
zyxclmm_drm {
compatible = “xlnx,zocl”;
status = “okay”;
reg = <0x0 0xA0000000 0x0 0x10000>;
};
};

12- Configure the linux rootfs by running the following command

petalinux-config -c rootfs

13- Go to the “user packages” menu and select the following packages

opencl-hpp-dev
opencl-headers-dev
packagegroup-petalinux-opencv
xrt
xrt-dev
zocl

14- Then build the peralinux project by running this command.

petalinux-build

15- The go to images/linux folder

cd images/linux

and run this command

petalinux-build –sdk

16- Then run the ./sdk.sh command and enter the full path of the linux_files folder that you created at the first phase.

17- Copy the following files from the image/linux folder into the linux_files/boot folder that you created in the first phase.

image.ub
zynqmp_fsbl.elf
pmufw.elf
bl31.elf
u-boot.elf

18- In the linux_files/boot folder create the linux.bif file containing the following lines

/* linux */

the_ROM_image:

{

[fsbl_config] a53_x64

[bootloader]

[pmufw_image]

[destination_device=pl]

[destination_cpu=a53-0, exception_level=el-3, trustzone]

[destination_cpu=a53-0, exception_level=el-2]

}

3- Create Platform

1- Create a folder named pfm in the ultra96v2-vitis-pkg folder that you created in the first step.

cd pfm

To create the ultra96v2 platform for Vitis. First, run the Vitis IDE and choose the pfm folder (that you created in the first step) as the workspace.

2- Create a new platform project by selecting “File–>New–>Platform Project…”. Choos “ultra96v2” as the project name and accept the default folder.

3- In the next window select the XSA option and press Next

4- Click on Brows… button and locate the ultra96v2.xsa file generated in the first step by Vivado, and then select the linux as Operating System and click Finish button.

5- Clock the Welcome window if it is open. Select “linux on psu_cortexa53” and configure the Linux domain as the following figure.

6- Press the right-click on the project name on the left panel and select Build Project.

4- Test

1- In the Vitis IDE, select “File–>New–>Application Project…” to create a new application.

2- Select vector_add as the Project name

3- Select the ultra96v2 [custom] platform in the next window

4- Press the Next button in the next window.

5- Select the Vector Addition as the template and press Finish button.

6- Select Hardware as the active build configuration from the menu on the right.

7- Build the project by pressing the right-click on the project name and selecting the Build project option.

8- Copy the content of the sd_card folder generated by the application project into an SD-CARD and boot the U;tra96v2 board.

9- Using putty open a serial terminal with the following configuration

10- login to the board by using root as both username and password. Then go to /run/media/mmcblk0p1 folder

11- Run the following commands to define the Xilinx XRT library

export XILINX_XRT=/usr

12- Run the application by running this command

./vector_add.exe binary_container_1.xclbin

Recommended Articles

29 Comments

  1. […] For a step-by-step tutorial for generating a Linux-based Platform for Ultra96v2 board please visit here. […]

  2. Hi,
    Thanks a lot for the tutorial, but where can i find the description of these steps, i would like to understand all the steps I am following
    Best Reh
    gards

      1. Can I follow the exact same steps including editing the device tree with the same values you have given for the ZCU102 board? Or I should change something?

  3. For zcu102, the process is easier as there is a prebuild BSP file at the Xilinx website at
    https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html

    You can follow most of the above process for zcu102. but you don’t need to
    change the “psu_uart_0” to “psu_uart_1” at step 5 in Linux section.

    1. Do i need to make the same changes to the device tree?

      1. Adding the following part should be enough

        &amba {
        zyxclmm_drm {
        compatible = “xlnx,zocl”;
        status = “okay”;
        };
        };

  4. I followed the exact same steps but i got the following error when i tied building the petalinux :

    ERROR: device-tree-xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0 do_compile: Error executing a python function in exec_python_func() autogenerated:

    The stack trace of python calls that resulted in this exception/failure was:
    File: ‘exec_python_func() autogenerated’, lineno: 2, function:
    0001:
    *** 0002:devicetree_do_compile(d)
    0003:
    File: ‘/tools/Xilinx/petalinux/components/yocto/source/aarch64/layers/core/meta/classes/devicetree.bbclass’, lineno: 131, function: devicetree_do_compile
    0127: if not(os.path.isfile(dtspath)) or not(dts.endswith(“.dts”) or devicetree_source_is_overlay(dtspath)):
    0128: continue # skip non-.dts files and non-overlay files
    0129: except:
    0130: continue # skip if can’t determine if overlay
    *** 0131: devicetree_compile(dtspath, includes, d)
    0132:}
    0133:
    0134:devicetree_do_install() {
    0135: for DTB_FILE in `ls *.dtb *.dtbo`; do
    File: ‘/tools/Xilinx/petalinux/components/yocto/source/aarch64/layers/core/meta/classes/devicetree.bbclass’, lineno: 119, function: devicetree_compile
    0115: dtcargs += [“-i”, i]
    0116: dtcargs += [“-o”, “{0}.{1}”.format(dtname, “dtbo” if isoverlay else “dtb”)]
    0117: dtcargs += [“-I”, “dts”, “-O”, “dtb”, “{0}.pp”.format(dts)]
    0118: bb.note(“Running {0}”.format(” “.join(dtcargs)))
    *** 0119: subprocess.run(dtcargs, check = True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
    0120:
    0121:python devicetree_do_compile() {
    0122: includes = expand_includes(“DT_INCLUDE”, d)
    0123: listpath = d.getVar(“DT_FILES_PATH”)
    File: ‘/tools/Xilinx/petalinux/components/yocto/source/aarch64/buildtools/sysroots/x86_64-petalinux-linux/usr/lib/python3.5/subprocess.py’, lineno: 398, function: run
    0394: raise
    0395: retcode = process.poll()
    0396: if check and retcode:
    0397: raise CalledProcessError(retcode, process.args,
    *** 0398: output=stdout, stderr=stderr)
    0399: return CompletedProcess(process.args, retcode, stdout, stderr)
    0400:
    0401:
    0402:def list2cmdline(seq):
    Exception: subprocess.CalledProcessError: Command ‘[‘dtc’, ‘-R’, ‘8’, ‘-b’, ‘0’, ‘-p’, ‘0x1000’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/altera’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/marvell’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/zte’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/apm’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/amd’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/mediatek’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/arm’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/broadcom’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/allwinner’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/exynos’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/scripts/dtc/include-prefixes’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/xilinx’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/synaptics’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/qcom’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/nvidia’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/include’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/socionext’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/actions’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/hisilicon’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/cavium’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/realtek’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/rockchip’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/../components/plnx_workspace/device-tree/device-tree’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/lg’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/amlogic’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/ti’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/sprd’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/freescale’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/renesas’, ‘-i’, ‘/Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work-shared/plnx-zynqmp/kernel-source/arch/arm64/boot/dts/al’, ‘-o’, ‘system-top.dtb’, ‘-I’, ‘dts’, ‘-O’, ‘dtb’, ‘system-top.dts.pp’]’ returned non-zero exit status 1

    Subprocess output:
    Error: /Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/system-user.dtsi:6.17-18 syntax error
    FATAL ERROR: Unable to parse input tree

    ERROR: device-tree-xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0 do_compile: Function failed: devicetree_do_compile
    ERROR: Logfile of failure stored in: /Vivado_Projects/zcu102-vitis-pkg/zcu102-petalinux/build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/temp/log.do_compile.12785
    ERROR: Task (/tools/Xilinx/petalinux/components/yocto/source/aarch64/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_compile) failed with exit code ‘1’

    1. It seems you have mistakes (typos) at line 6 in system-user.dtsi file.
      check for semicolons, parenthesis
      and remember to only add the following code at the end of the file

      &amba {
      zyxclmm_drm {
      compatible = “xlnx,zocl”;
      status = “okay”;
      };
      };

      1. you are perfect, thanks a lot

      2. I reached the step of building the vector_add project but i get the following error after build :
        make all
        Generating bif file for the system project
        Executing command ‘::scw::generate_bif -xpfm /Vivado_Projects/zcu102-vitis-pkg/pfm/zcu102/export/zcu102/zcu102.xpfm -domains linux_domain -bifpath /Vivado_Projects/zcu102-vitis-pkg/pfm/vector_add_system/Debug/system.bif’ on XSCT
        sdcard_gen –xpfm /Vivado_Projects/zcu102-vitis-pkg/pfm/zcu102/export/zcu102/zcu102.xpfm –sys_config zcu102 –bif /Vivado_Projects/zcu102-vitis-pkg/pfm/vector_add_system/Debug/system.bif –no_bitstream –sd_file /Vivado_Projects/zcu102-vitis-pkg/pfm/vector_add/Hardware/vector_add.exe
        SD data file does not exist: /Vivado_Projects/zcu102-vitis-pkg/pfm/vector_add/Hardware/vector_add.exe
        makefile:36: recipe for target ‘sd_card’ failed

        make: *** [sd_card] Error 1ortexa53_0/libsrc/xilpm_v3_0/src line 1788 C/C++ Problem

        can u please assist me on this

  5. 1- check carefully steps 16, 17, 18 in “2- Linux OS”
    2- check carefully step 5 in “3- Create Platform”

    1. make: *** [sd_card] Error 1ortexa53_0/libsrc/xilpm_v3_0/src line 1788 C/C++ Problem

      Debe verificar que tenga los drivers open cl y el runtime XIlinx instalados. (https://www.hackster.io/news/microzed-chronicles-vitis-acceleration-creating-a-vm-setup-363946fb4ede)

      Luego, en el paso 7 de la sección 4-Test del tutorial, debe verificar que lo realice de la forma correcta. Dar build ubicado correctamente sobre el archivo que muestra la figura.

  6. Using Ubuntu 16.04 and followed your steps still to “write_hw_platform -include_bit ultra96v2.xsa”, then I got a Warning and error message.

    “WARNING: [Project 1-971] Hardware Platform (Shell) metadata attributes vendor, board, name, version will be populated from project properties platform.vendor (xilinx), platform.board_id (ultra96), platform.name () and platform.version (0.0). The values from PFM_NAME property (vendor:lib:ultra96v2_design:1.0) on the BD will be over-ridden.

    ERROR: [Common 17-53] User Exception: Project property platform.name needs to be set before generating a XSA.”

    1. I found am alternative way, use the GUI and export the hardware and select the include bitstream instead of the command.

  7. I followed this process and I could compile the vadd example. However, when I turned the board ON, D8 LED on the mezzanine board is blinking and the board is not booting up. I have another image with which the board is booting up and D8 is also not blinking.

  8. Is there any tutorial how to build the vitis base platform for the zynq 7000?

  9. Hi Mohammad, thank you for your article, it’s really useful for me.
    May I know what does zyxclmm_drm refer to in the device tree part?
    I created a module at the same address at 0xA0000000, and I am learning how to write the device into the device tree, so I am curious about this.
    Thank you in advance.

    1. zyxclmm_drm refers to the device-tree entry to add the zocl driver for Xilinx Runtime (XRT).

      1. Thank you very much for your kind reply and I am really thankful for your sharing!

  10. Hi Mohammad,
    thank you for your step by step tutorial. It’s really useful for me. I followed the exact the same steps but I was not able to run linux on my device. It looks like it got stuck in boot. I tried to download it via JTAG (petalinux-boot –jtag –u-boot –fpga –pmufw) and I got the following error: Memory write error at 0x8000000. MMU fault at VA 0x8000000. Translation fault, second level
    invoked from within
    “::tcf::eval -progress {
    apply {{info} {
    switch — [lindex $info 0] {
    “info” {
    puts -nonewline “\r[lindex $info 1]”
    }
    “warning” {
    puts “\n[lindex $info 1]”
    }
    “data” {
    puts -nonewline “\r[lindex $info 1] of [lindex $info 2] complete”
    }
    “done” {
    puts “\n[lindex $info 1]”
    }
    }
    flush stdout
    ::xsdb::abort_check
    }}} {::tcf::cache_enter tcfchan#0 {tcf_cache_eval {download_cache_client ::tcfclient#0::arg}}}”
    (procedure “::tcf::cache_eval_with_progress” line 2)
    invoked from within
    “::tcf::cache_eval_with_progress $params(chan) [list download_cache_client $argvar] {
    apply {{info} {
    switch — [lindex $info 0] {
    “info” …”
    (procedure “dow” line 78)
    invoked from within
    “dow “/home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/u-boot.elf””
    (file “/tmp/tmp.oRox8Bhsl5” line 28)
    INFO: The XSDB log is as follows
    attempting to launch hw_server

    ****** Xilinx hw_server v2019.2
    **** Build date : Oct 23 2019 at 23:11:29
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

    INFO: hw_server application started
    INFO: Use Ctrl-C to exit hw_server application

    INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121

    100% 5MB 0.9MB/s 00:05
    Downloading Program — /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/pmufw.elf
    section, .vectors.reset: 0xffdc0000 – 0xffdc0007
    section, .vectors.sw_exception: 0xffdc0008 – 0xffdc000f
    section, .vectors.interrupt: 0xffdc0010 – 0xffdc0017
    section, .vectors.hw_exception: 0xffdc0020 – 0xffdc0027
    section, .text: 0xffdc0050 – 0xffdd11bb
    section, .rodata: 0xffdd11bc – 0xffdd32d3
    section, .data: 0xffdd32d4 – 0xffdd75cb
    section, .sdata2: 0xffdd75cc – 0xffdd75cf
    section, .sdata: 0xffdd75d0 – 0xffdd75cf
    section, .sbss: 0xffdd75d0 – 0xffdd75cf
    section, .bss: 0xffdd75e0 – 0xffddb60f
    section, .srdata: 0xffddb610 – 0xffddbf33
    section, .stack: 0xffddbf34 – 0xffddcf37
    section, .xpbr_serv_ext_tbl: 0xffddf6e0 – 0xffddfadf
    100% 0MB 0.0MB/s 00:02
    Setting PC to Program Start Address 0xffdd03dc
    Successfully downloaded /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/pmufw.elf
    Downloading Program — /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/zynqmp_fsbl.elf
    section, .text: 0xfffc0000 – 0xfffce353
    section, .init: 0xfffce380 – 0xfffce3b3
    section, .fini: 0xfffce3c0 – 0xfffce3f3
    section, .note.gnu.build-id: 0xfffce3f4 – 0xfffce417
    section, .rodata: 0xfffce440 – 0xfffce8b7
    section, .sys_cfg_data: 0xfffce8c0 – 0xfffcf117
    section, .mmu_tbl0: 0xfffd0000 – 0xfffd000f
    section, .mmu_tbl1: 0xfffd1000 – 0xfffd2fff
    section, .mmu_tbl2: 0xfffd3000 – 0xfffd6fff
    section, .data: 0xfffd7000 – 0xfffd83b7
    section, .sbss: 0xfffd83b8 – 0xfffd83bf
    section, .bss: 0xfffd83c0 – 0xfffda47f
    section, .heap: 0xfffda480 – 0xfffda87f
    section, .stack: 0xfffda880 – 0xfffdc87f
    section, .dup_data: 0xfffdc880 – 0xfffddc37
    section, .handoff_params: 0xfffe9e00 – 0xfffe9e87
    section, .bitstream_buffer: 0xffff0040 – 0xfffffc3f
    100% 0MB 0.0MB/s 00:09
    Setting PC to Program Start Address 0xfffc0000
    Successfully downloaded /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/zynqmp_fsbl.elf
    Downloading Program — /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/u-boot.elf
    section, .data: 0x08000000 – 0x080863ad
    aborting, 1 pending requests…
    Failed to download /home/vladimir/vitis/ultra96v2_vitis_pkg/ultra96v2-petalinux/images/linux/u-boot.elf

    What can cause this error?

    Thank you for your attention,

    Vladimir

    1. Are you using the same board which is Ultra96v2?

      1. yes, I have ultra96v2, label 1950 (2019, week 50)

      2. If I create SD from demo provided by Avnet then board starts and works correctly but if I try to build the image by myself it doesn’t.

      3. It looks like zynqmp_fsbl.elf is incorrectly generated from zynqmp template. I replaced it with the zynqmp_fsbl.elf file which was generated from ultra96v2_oob_2019_2.bsp and everything works. The question is why the zynqmp_fsbl.elf file from template was incorrectly generated by petalinux and how to fix it.

  11. Thank you Mohammad for posting this detailed step-by-step tutorial. I am using version 2020.1 of Petalinux and have encountered two problems, one solved and one that led to failure:

    → step 8: DMA size is not in Driver Options but in Library Routines -> DMA Contiguous Memory Allocator (256 to be changed to 1024). This seems OK.

    → step 14: petalinux-build has one error related to a python call: here is the log:

    ERROR: libmali-xlnx-r9p0-01rel0-r0 do_package: Error executing a python function in exec_python_func() autogenerated:

    The stack trace of python calls that resulted in this exception/failure was:
    File: ‘exec_python_func() autogenerated’, lineno: 2, function:
    0001:
    *** 0002:do_package(d)
    0003:
    File: ‘/home/casu/testvitis/ultra96v2-vitis-pkg/ultra96v2-petalinux/components/yocto/layers/core/meta/classes/package.bbclass’, lineno: 2309, function: do_package
    2305:
    2306:do_package[dirs] = “${SHLIBSWORKDIR} ${PKGDESTWORK} ${D}”
    2307:do_package[vardeps] += “${PACKAGEBUILDPKGD} ${PACKAGESPLITFUNCS} ${PACKAGEFUNCS} ${@gen_packagevar(d)}”
    2308:addtask package after do_install
    *** 2309:
    2310:SSTATETASKS += “do_package”
    2311:do_package[cleandirs] = “${PKGDEST} ${PKGDESTWORK}”
    2312:do_package[sstate-plaindirs] = “${PKGD} ${PKGDEST} ${PKGDESTWORK}”
    2313:do_package_setscene[dirs] = “${STAGING_DIR}”
    Exception: FileNotFoundError: [Errno 2] No such file or directory: ‘/home/casu/testvitis/ultra96v2-vitis-pkg/ultra96v2-petalinux/build/tmp/work/zynqmp-xilinx-linux/libmali-xlnx/r9p0-01rel0-r0/pkgdata/shlibs2/libmali-xlnx.list’

    ERROR: Logfile of failure stored in: /home/casu/testvitis/ultra96v2-vitis-pkg/ultra96v2-petalinux/build/tmp/work/zynqmp-xilinx-linux/libmali-xlnx/r9p0-01rel0-r0/temp/log.do_package.27436
    ERROR: Task (/home/casu/testvitis/ultra96v2-vitis-pkg/ultra96v2-petalinux/components/yocto/layers/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb:do_package) failed with exit code ‘1’

    Would you please comment as I couldn’t find a solution? I’d really appreciate!

  12. Problem solved by itself: I had to run petalinux-build again and again: each time a new error appeared, which was solved by the next attempt until all errors disappeared, Go figure…

  13. New problem, not solved this time: when I run the script sdk.sh (step 16) I get this message:

    SDK could not be set up. Relocate script unable to find ld-linux.so. Abort!

    I think it might have to do with the “/lib” directory, because this is where the script is looking for the library while I guess it has to be somewhere in the sysroot directory. This is a snippet of what I get when I run “sh -x ./sdk.sh”

    + real_env_setup_script=
    ++ ls /home/casu/testvitis/ultra96v2-vitis-pkg/linux_files/environment-setup-aarch64-xilinx-linux
    + for env_setup_script in ‘`ls $target_sdk_dir/environment-setup-*`’
    + grep -q OECORE_NATIVE_SYSROOT= /home/casu/testvitis/ultra96v2-vitis-pkg/linux_files/environment-setup-aarch64-xilinx-linux
    + sed -e s:/opt/petalinux/2020.1:/home/casu/testvitis/ultra96v2-vitis-pkg/linux_files:g -i /home/casu/testvitis/ultra96v2-vitis-pkg/linux_files/environment-setup-aa
    rch64-xilinx-linux
    + ‘[‘ -n ” ‘]’
    + xargs –version
    ++ cat /home/casu/testvitis/ultra96v2-vitis-pkg/linux_files/environment-setup-aarch64-xilinx-linux
    ++ grep OECORE_NATIVE_SYSROOT=
    ++ cut -d= -f2
    ++ tr -d ‘”‘
    + native_sysroot=
    ++ find /lib -name ‘ld-linux*’
    + dl_path=
    + ‘[‘ ” = ” ‘]’
    + echo ‘SDK could not be set up. Relocate script unable to find ld-linux.so. Abort!’
    + exit 1

    Any suggestions?

    Thanks a lot

  14. For whom may get the same issue.

    I had an issue with step 5 and I fixed it with the following:

    5- In the “DTG Settings –>Kernel Bootargs–>” disable generate boot args automatically” option. then in the “user set kernel bootargs” enter the following arguments

    (earlycon clk_ignore_unused root=/dev/ram rw) ==> Didn’t work for me
    earlycon clk_ignore_unused console=ttyPS0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait) ==> Worked for me

Leave a Reply

Sale on now | Up to 80% OFF on All HLS Courses

2 day left!

X
%d bloggers like this: