Goal | Increasing clock frequency |
Approach | Loop splitting |
Benefits | Faster design using High-level Synthesis |
Credit |
Loop splitting is a technique to increase the frequency operation of a pipelined loop. The following example shows this situation.
Consider the following code as an example. This code calculate the sigmoid function which is used in neural-networks, machine-learning, logic regression, etc.
for (u32 i = 0; i < n; i++) { #pragma HLS PIPELINE DATA_TYPE yz = y_local[i]*z[i]; DATA_TYPE f_element_tmp; f += C_local[i]*log(1+exp(-yz)); }
After synthesising this loop with period=10nse the estimated latency and period are 4165 and 14.73, respectively. The estimated frequency is greater than the required frequency which is 100Mhz.
Therefor with the frequency of 66Mhz, the loop takes 62475 nsec to finish.
By splitting this loop into two parts the period reduces to 8.41 and the latency increases to 6215.
So with the frequency of 100 Mhz it takes 6215 nsec and with 111.11 Mhz it takes 55935 nsec.
for (int i = 0; i < DATA_LENGTH; i++) { #pragma HLS PIPELINE DATA_TYPE yz = y[i]*x[i]; DATA_TYPE f_element_tmp; f_local_array[i] = C[i]*log(1+exp(-yz)); } for (int i = 0; i < DATA_LENGTH; i++) { #pragma HLS PIPELINE f_local += f_local_array[i]; }